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LTC2226 Schematic ( PDF Datasheet ) - Linear Technology

Teilenummer LTC2226
Beschreibung 65/40/25Msps Low Power 3V ADCs
Hersteller Linear Technology
Logo Linear Technology Logo 




Gesamt 24 Seiten
LTC2226 Datasheet, Funktion
FEATURES
Sample Rate: 65Msps/40Msps/25Msps
Single 3V Supply (2.7V to 3.4V)
Low Power: 205mW/120mW/75mW
71dB SNR up to 70MHz Input
80dB SFDR up to 140MHz Input
No Missing Codes
Flexible Input: 1VP-P to 2VP-P Range
575MHz Full Power Bandwidth S/H
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Pin Compatible Family
80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit)
65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit)
40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit)
25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)
10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)
32-Pin (5mm × 5mm) QFN Package
U
APPLICATIO S
Wireless and Wired Broadband Communication
Imaging Systems
Ultrasound
Spectral Analysis
Portable Instrumentation
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
ANALOG
INPUT
+
INPUT
S/H
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
CLOCK/DUTY
CYCLE
CONTROL
CLK
LTC2228/LTC2227/LTC2226
12-Bit, 65/40/25Msps
Low Power 3V ADCs
DESCRIPTIO
The LTC®2228/LTC2227/LTC2226 are 12-bit 65Msps/
40Msps/25Msps, low power 3V A/D converters designed
for digitizing high frequency, wide dynamic range signals.
The LTC2228/LTC2227/LTC2226 are perfect for demand-
ing imaging and communications applications with AC
performance that includes 71dB SNR and 80dB SFDR for
signals well beyond the Nyquist frequency.
DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.25LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.3V
logic.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
OUTPUT
DRIVERS
OVDD
D11
D0
OGND
LTC2228: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
72
71
70
69
222876 TA01
68
0 50 100 150 200
INPUT FREQUENCY (MHz)
2228 G09
222876f
1






LTC2226 Datasheet, Funktion
LTC2228/LTC2227/LTC2226
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2228: Typical INL, 2V Range,
65Msps
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
0
1024
2048
CODE
3072
4096
2228 G01
LTC2228: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30
FREQUENCY (MHz)
2228 G04
LTC2228: 8192 Point 2-Tone FFT,
fIN = 28.2MHz and 26.8MHz, –1dB,
2V Range, 65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30
FREQUENCY (MHz)
2228 G07
6
LTC2228: Typical DNL, 2V Range,
65Msps
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
0
1024
2048
CODE
3072
4096
2228 G02
LTC2228: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30
FREQUENCY (MHz)
2228 G05
LTC2228: Grounded Input
Histogram, 65Msps
70000
60000
61496
50000
40000
30000
20000
10000
0
2123
2042
2043
CODE
1910
2044
2228 G08
LTC2228: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25
FREQUENCY (MHz)
30
2228 G03
LTC2228: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30
FREQUENCY (MHz)
2228 G06
LTC2228: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
72
71
70
69
68
0 50 100 150 200
INPUT FREQUENCY (MHz)
2228 G09
222876f

6 Page









LTC2226 pdf, datenblatt
LTC2228/LTC2227/LTC2226
PI FU CTIO S
AIN+ (Pin 1): Positive Differential Analog Input.
AIN- (Pin 2): Negative Differential Analog Input.
REFH (Pins 3, 4): ADC High Reference. Short together and
bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 5, 6 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
REFL (Pins 5, 6): ADC Low Reference. Short together and
bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 3, 4 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF
ceramic chip capacitors.
GND (Pin 8): ADC Power Ground.
CLK (Pin 9): Clock Input. The input sample starts on the
positive edge.
SHDN (Pin 10): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to VDD results in normal operation with the
outputs at high impedance. Connecting SHDN to VDD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to VDD and OE to VDD
results in sleep mode with the outputs at high impedance.
OE (Pin 11): Output Enable Pin. Refer to SHDN pin
function.
NC (Pins 12, 13): Do Not Connect These Pins.
D0 – D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26,
27): Digital Outputs. D11 is the MSB.
OGND (Pin 20): Output Driver Ground.
OVDD (Pin 21): Positive Supply for the Output Drivers.
Bypass to ground with 0.1µF ceramic chip capacitor.
OF (Pin 28): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
straight binary output format and turns the clock duty
cycle stabilizer off. 1/3 VDD selects straight binary output
format and turns the clock duty cycle stabilizer on. 2/3 VDD
selects 2’s complement output format and turns the clock
duty cycle stabilizer on. VDD selects 2’s complement
output format and turns the clock duty cycle stabilizer off.
SENSE (Pin 30): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±VSENSE. ±1V is the largest valid input range.
VCM (Pin 31): 1.5V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad) (Pin 33): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
12
222876f

12 Page





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