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PDF ADG5206 Data sheet ( Hoja de datos )
| Número de pieza | ADG5206 | |
| Descripción | 8-/16-Channel Multiplexers | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
Latch-up proof
3.5 pF off source capacitance
Off drain capacitance
ADG5206: 64 pF
ADG5207: 33 pF
0.35 pC typical charge injection
±0.02 nA on channel leakage
Low on resistance: 155 Ω typical
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
VSS to VDD analog signal range
Human body model (HBM) ESD rating
ADG5206: 8 kV all pins
ADG5207: 8 kV I/O port to supplies
APPLICATIONS
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Battery monitoring
Communication systems
GENERAL DESCRIPTION
The ADG5206 and ADG5207 are monolithic CMOS analog
multiplexers comprising 16 single channels and 8 differential
channels, respectively. The ADG5206 switches one of sixteen
inputs to a common output, as determined by the 4-bit binary
address lines, A0, A1, A2, and A3. The ADG5207 switches one
of eight differential inputs to a common differential output, as
determined by the 3-bit binary address lines, A0, A1, and A2.
An EN input on both devices enables or disables the device. When
EN is low, the device is disabled and all channels switch off. The
ultralow capacitance and charge injection of these switches make
them ideal solutions for data acquisition and sample-and-hold
applications, where low glitch and fast settling are required. Fast
switching speed coupled with high signal bandwidth make these
devices suitable for video signal switching.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
power supplies. In the off condition, signal levels up to the
supplies are blocked.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
High Voltage, Latch-Up Proof,
8-/16-Channel Multiplexers
ADG5206/ADG5207
FUNCTIONAL BLOCK DIAGRAMS
ADG5206
S1
D
S16
1-OF-16
DECODER
A0 A1 A2 A3 EN
Figure 1.
ADG5207
S1A
DA
S8A
S1B
S8B
1-OF-8
DECODER
DB
A0 A1 A2 EN
Figure 2.
The ADG5206/ADG5207 do not have VL pins; instead, an on-chip
voltage generator generates the logic power supply internally.
PRODUCT HIGHLIGHTS
1. Trench Isolation Guards Against Latch-Up. A dielectric trench
separates the P and N channel transistors to prevent latch-up
even under severe overvoltage conditions.
2. Optimal switch design for low charge injection, low switch
capacitance, and low leakage currents.
3. The ADG5206 achieves 8 kV HBM ESD specification on
all external pins, while the ADG5207 achieves 8 kV on the
I/O port to supply pins, 2 kV on the I/O port to I/O port
pins, and 8 kV on all other pins.
4. Dual-Supply Operation. For applications where the analog
signal is bipolar, the ADG5206/ADG5207 can be operated
from dual supplies of up to ±22 V.
5. Single-Supply Operation. For applications where the
analog signal is unipolar, the ADG5206/ADG5207 can be
operated from a single rail power supply of up to 40 V.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADG5206/ADG5207
Parameter
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
25°C
−40°C to −40°C to −40°C to
+60°C
+85°C
+125°C Unit
±0.005
nA typ
Match Between Channels, ΔLeakage, IS (Off)1
Drain Off Leakage, ID (Off )
±0.1
0.01
±0.15
±0.2
±0.4
0.015
nA max
nA typ
ADG5206
ADG5207
Match Between Channels, ΔLeakage,
ID (Off ), ADG5207 Only
Channel On Leakage, ID (On), IS (On)
±0.02
±0.1
±0.02
±0.1
0.015
±0.25
±0.25
±0.6
±0.4
±3.3
±1.7
0.015
nA typ
nA max
nA typ
nA max
nA typ
ADG5206
ADG5207
Match Between Channels, ΔLeakage,
ID(On), IS (On)2
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS3
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
±0.02
nA typ
±0.1 ±0.25
±0.6
±3.3
nA max
±0.02
nA typ
±0.1 ±0.2 ±0.4 ±1.7 nA max
0.01 0.03 nA typ
±0.002
3
2.0 V min
0.8 V max
µA typ
±0.1 µA max
pF typ
185 ns typ
240 270 290 320 ns max
175 ns typ
230 245 255 270 ns max
135 ns typ
185 205 220 245 ns max
75 ns typ
27 ns min
0.45 pC typ
Off Isolation
±4 ±4 pC typ
−90 dB typ
Channel-to-Channel Crosstalk
−76
dB typ
−3 dB Bandwidth
ADG5206
ADG5207
Insertion Loss
65
145
5.6
MHz typ
MHz typ
dB typ
CS (Off )
3.3
pF typ
Test Conditions/Comments
VDD = +22 V, VSS = −22 V
VS = ±15 V, VD = 15 V;
see Figure 33
VS = ±15 V, VD = 15 V;
see Figure 33
VS = VD = ±15 V;
see Figure 34
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 35
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 37
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
VS = ±10 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF,
f = 1 MHz; see Figure 39
RL = 50 Ω, CL = 5 pF,
f = 1 MHz; see Figure 40
RL = 50 Ω, CL = 5 pF;
see Figure 41
RL = 50 Ω, CL = 5 pF,
f = 1 MHz; see Figure 41
VS = 0 V, f = 1 MHz
Rev. A | Page 5 of 28
5 Page 
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 7.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Peak Current, Sx, D, or Dx Pins
ADG5206
ADG5207
Continuous Current, Sx, D, or Dx
Pins2
Temperature Range
Operating
Storage
Junction Temperature
Thermal Impedance, θJA
28-Lead TSSOP (4-Layer Board)
32-Lead LFCSP (4-Layer Board)
Reflow Soldering Peak
Temperature, Pb Free
HBM ESD
(ESDA/JEDEC JS-001-2011)
ADG5206
All Pins
ADG5207
I/O Port to Supplies
I/O Port to I/O Port
All Other Pins
Rating
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
140 mA (pulsed at 1 ms, 10%
duty cycle maximum)
105 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Data + 15%
−40°C to +125°C
−65°C to +150°C
150°C
67.7°C/W
27.27°C/W
As per JEDEC J-STD-020
8 kV
8 kV
2 kV
8 kV
1 Overvoltages at the Ax, EN, Sx, D, and Dx pins are clamped by internal
diodes. Limit current to the maximum ratings given.
2 See Table 5 and Table 6.
ADG5206/ADG5207
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
Rev. A | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ADG5206.PDF ] | |
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