Datenblatt-pdf.com


ICS307-02 Schematic ( PDF Datasheet ) - Integrated Circuit Systems

Teilenummer ICS307-02
Beschreibung SERIALLY PROGRAMMABLE CLOCK SOURCE
Hersteller Integrated Circuit Systems
Logo Integrated Circuit Systems Logo 




Gesamt 9 Seiten
ICS307-02 Datasheet, Funktion
ICS307-01/02
SERIALLY PROGRAMMABLE CLOCK SOURCE
Description
The ICS307-01 and ICS307-02 are versatile serially
programmable clock sources which take up very little
board space. They can generate any frequency from 6
to 200 MHz and have a second configurable output.
The outputs can be reprogrammed on the fly and will
lock to a new frequency in 10 ms or less. Smooth
transitions (in which the clock duty cycle remains near
50%) are guaranteed if the output divider is not
changed.
The devices includes a PDTS pin which tri-states the
output clocks and powers down the entire chip.
The ICS307-02 features a default clock output at
start-up and is recommended for all new designs.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
For applications which require defined input to output
skew, use the ICS527-01.
Features
Packaged in 16-pin (150 mil wide) SOIC
ICS307M-02 and -02I available in Pb (lead) free
package
Highly accurate frequency generation
Serially programmable: user determines the output
frequency via a 3 wire interface
Eliminates need for custom quartz
Input crystal frequency of 5 - 27 MHz
Output clock frequencies up to 200 MHz
Power down tri-state mode
Very low jitter
Operating voltage of 3.3 V or 5 V
25 mA drive capability at TTL levels
Industrial temperature version available
Block Diagram
SCLK
DATA
STROBE
X1/ICLK
Crystal or
clock input
X2
TTL
9 V8:V0
Shift
Register
2
3
2
7
C1:C0
S2:S0
F1:F0
R6:R7
Crystal
Oscillator
Reference
Divider
Optional crystal capacitors
VDD
VCO
Divider
Phase Comparator,
Charge Pump, and
Loop Filter
VCO
GND
Output
Divider
3
S2:S0
Function
Select
3
F1:F0
CLK1
PDTS
CLK2
MDS 307-01/02 F
1
Revision 121304
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com






ICS307-02 Datasheet, Funktion
ICS307-01/02
SERIALLY PROGRAMMABLE CLOCK SOURCE
Programming Example
To generate 66.66 MHz from a 14.31818 MHz input, the RDW should be 59, the VDW should be 276, and
the Output Divide is 2. Selecting the minimum internal load capacitance, CMOS duty cycle, and CLK2 to be
OFF means that the following three bytes are sent to the ICS307:
00110001
Byte 1
10001010
Byte 2
00111011
Byte 3
As show in Figure 2, after these 24 bits are clocked into the ICS307, taking STROBE high will send this
data to the internal latch and the CLK output will lock within 10 ms.
Note: If STROBE is in the high state and SCLK is pulsed, DATA is clocked directly to the internal latch and
the output conditions will change accordingly. Although this will not damage the ICS307, it is recommended
that STROBE be kept low while DATA is being clocked into the ICS307 in order to avoid unintended
changes on the output clocks.
AC Parameters for Writing to the ICS307
Parameter
tSETUP
tHOLD
tW
tS
Condition
Setup time
Hold time after SCLK
Data wait time
Strobe pulse width
SCLK Frequency
DATA C1
tsetup
C0 TTL F1
thold
R1 R0
Min.
10
10
10
40
Max.
50
Units
ns
ns
ns
ns
MHz
SCLK
STROBE
tw ts
Figure 2. Timing Diagram for Programming the ICS307
External Components/Crystal Selection
The ICS307 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be connected
close to the ICS307 to minimize lead inductance. A 33terminating resistor can be used in series with CLK1 and
CLK2 outputs. A parallel resonant, fundamental mode crystal with a load (correlation) capacitance of C should be
used, where C is the value calculated from Table 4. For crystals with a specified load capacitance greater than C,
additional crystal capacitors may be connected from each of the pins X1 and X2 to ground as shown in the Block
Diagram on page 1. The value (in pF) of these crystal caps should be = (CL-C)*2, where CL is the crystal load
capacitance in pF and C is the capacitance value from Table 4. These external capacitors are only required for
applications where the exact frequency is critical. For a clock input, connect to X1 and leave X2 unconnected (no
capacitors on either pin).
MDS 307-01/02 F
6
Revision 121304
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

6 Page







SeitenGesamt 9 Seiten
PDF Download[ ICS307-02 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ICS307-01SERIALLY PROGRAMMABLE CLOCK SOURCEIDT
IDT
ICS307-01SERIALLY PROGRAMMABLE CLOCK SOURCEIntegrated Circuit Systems
Integrated Circuit Systems
ICS307-02SERIALLY PROGRAMMABLE CLOCK SOURCEIDT
IDT
ICS307-02SERIALLY PROGRAMMABLE CLOCK SOURCEIntegrated Circuit Systems
Integrated Circuit Systems
ICS307-03SERIALLY PROGRAMMABLE CLOCK SOURCEIntegrated Circuit Systems
Integrated Circuit Systems

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche