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TC1182 Schematic ( PDF Datasheet ) - Infineon Technologies

Teilenummer TC1182
Beschreibung 32-Bit Single-Chip Microcontroller
Hersteller Infineon Technologies
Logo Infineon Technologies Logo 




Gesamt 30 Seiten
TC1182 Datasheet, Funktion
32-Bit
Microcontroller
TC1782 / TC1182
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.1 2011-06
Microcontrollers






TC1182 Datasheet, Funktion
TC1782 / TC1182
Data Sheet
3 V 1.1, 2011-06

6 Page









TC1182 pdf, datenblatt
TC1782 / TC1182
Summary of Features
• Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
• High performing on-chip bus structure
– 64-bit Local Memory Buses between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (LFI Bridge)
• Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Three High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– One serial Micro Second Bus interface (MSC) for serial port expansion to external
power devices
– One High-Speed Micro Link interface (MLI) for serial inter-processor
communication
– One MultiCAN Module with 3 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell
Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
• 32 analog input lines for ADC
– 2 independent kernels (ADC0 and ADC1)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
• 4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
• 86 digital general purpose I/O lines (GPIO), 4 input lines
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
• Dedicated Emulation Device chip available (TC1782 / TC1182ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
• Power Management System
• Clock Generation Unit with PLL
Data Sheet
5 V 1.1, 2011-06

12 Page





SeitenGesamt 30 Seiten
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