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ISL80015A Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer ISL80015A
Beschreibung Compact Synchronous Buck Converters
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 16 Seiten
ISL80015A Datasheet, Funktion
DATASHEET
Compact Synchronous Buck Converters
ISL80020, ISL80020A, ISL80015, ISL80015A
The ISL80020, ISL80020A, ISL80015 and ISL80015A are highly
efficient, monolithic, synchronous step-down DC/DC converters
that can deliver up to 2A of continuous output current from a 2.7V
to 5.5V input supply. They use peak current mode control
architecture to allow very low duty cycle operation. They operate
at either 1MHz or 2MHz switching frequency, thereby providing
superior transient response and allowing for the use of small
inductors. They have excellent stability.
Features
• VIN range 2.7V to 5.5V
• IOUT maximum is 1.5A or 2A (see Table 1 on page 2)
• Switching frequency is 1MHz or 2MHz (see Table 1 on page 2)
• Overcurrent and short circuit protection
• Over-temperature/thermal protection
The ISL80020, ISL80020A, ISL80015 and ISL80015A integrate
very low rDS(ON) MOSFETs in order to maximize efficiency. In
addition, since the high-side MOSFET is a PMOS, the need for a
Boot capacitor is eliminated, thereby reducing external
component count. They can operate at 100% duty cycle
(at 1MHz).
The device is configured in PWM (pulse width modulation) for
fast transient response, which helps reduce the output noise
and RF interference.
• Negative current protection
• Power-good and enable
• 100% duty cycle (1MHZ)
• Internal soft-start and soft-stop
• VIN undervoltage lockout and VOUT overvoltage protection
• Up to 95% peak efficiency
Applications
These devices are offered in a space saving 8 pin 2mmx2mm
TDFN lead free package with exposed pad for improved thermal
performance. The complete converter occupies less than
64mm2 area.
• General purpose POL
• Industrial, instrumentation, and medical equipment
• Telecom and networking equipment
• Game console
VIN
GND
EN
PG
+2.7V...+5.5V
C1
22µF
1 VIN
2 EN
ISL80015, ISL80020
3 SGND
4 PG
EPAD
9
L1
PHASE 8
PGND 7
+1.8V/2A
C2
22µF
NC 6
FB 5
0.6V
C3
22pF
R1
200kΩ 1%
R2
100kΩ 1%
VOUT
GND
R1
=
R2
V---V--F--O--B---
1
(EQ. 1)
FIGURE 1. TYPICAL APPLICATION CIRCUIT CONFIGURATION
100
90
80
70
2.5VOUT
1.5VOUT
1.8VOUT
3.3VOUT
60
50
400.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
OUTPUT LOAD (A)
FIGURE 2. EFFICIENCY vs LOAD, fSW = 2MHz, VIN = 5V, TA = +25°C
February 17, 2015
FN6692.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.






ISL80015A Datasheet, Funktion
ISL80020, ISL80020A, ISL80015, ISL80015A
Absolute Maximum Ratings
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms)
PHASE . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6V (DC) or 7V (20ms)
EN, PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
Junction Temperature Range at 0A . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
ESD Rating
Human Body Model (Tested per JESD22-JS-001) . . . . . . . . . . . . . . . . 4kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . . 2kV
Latch-up (Tested per JESD78D, Class 2, Level A) . . . ± 100mA at +125°C
Thermal Information
Thermal Resistance (Typical, Notes 4, 5) JA (°C/W) JC (°C/W)
2x2 TDFN Package . . . . . . . . . . . . . . . . . . .
71
7
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 2A
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications TJ = -40°C to +125°C, VIN = 2.7V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
MAX
TYP (Note 6) UNITS
INPUT SUPPLY
VIN Undervoltage Lockout Threshold
VUVLO
Rising, no load
Falling, no load
2.5 2.7 V
2.2 2.4
V
Quiescent Supply Current
Shutdown Supply Current
OUTPUT REGULATION
IVIN fSW = 1MHz, no load at the output
fSW = 2MHz, no load at the output
ISD VIN = 5.5V, EN = low
7 15 mA
10 22 mA
1.2 10 µA
Feedback Voltage
VFB Bias Current
Line Regulation
Load Regulation
VFB
TJ = -40°C to +125°C
IVFB VFB = 2.7V, TJ = -40°C to +125°C
VIN = VO + 0.5V to 5.5V (nominal 3.6V)
TJ = -40°C to +125°C
See (Note 7)
0.594
0.589
-350
-0.32
0.600
50
-0.05
< -0.2
0.606
0.606
350
0.28
V
V
nA
%/V
%/A
Soft-start Ramp Time Cycle (Note 7)
1 ms
PROTECTIONS
Positive Peak Current Limit
Thermal Shutdown
IPLIMIT
2A application (VIN = 3.6V)
1.5A application (VIN = 3.6V)
Temperature rising
2.8 3.18 3.6 A
2.1 2.5 2.9 A
150 °C
Thermal Shutdown Hysteresis (Note 7)
Temperature falling
25 °C
COMPENSATION
Error Amplifier Transconductance
(Note 7)
40 µA/V
Transresistance
RT
0.24
0.3
0.40
Ω
PHASE
P-channel MOSFET ON-resistance
N-channel MOSFET ON-resistance
VIN = 5V, IO = 200mA
VIN = 5V, IO = 200mA
117 mΩ
86 mΩ
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ISL80015A pdf, datenblatt
ISL80020, ISL80020A, ISL80015, ISL80015A
Theory of Operation
The device is a step-down switching regulator optimized for battery
powered applications. It operates at a high switching frequency
(1MHz or 2MHz), which enables the use of smaller inductors
resulting in small form factor, while also providing excellent
efficiency. The quiescent current is typically only 5µA when the
regulator is shut down.
PWM Control Scheme
The device employs the current-mode pulse-width modulation
(PWM) control scheme for fast transient response and
pulse-by-pulse current limiting. See “Functional Block Diagram” on
page 4. The current loop consists of the oscillator, the PWM
comparator, current sensing circuit and the slope compensation for
the current loop stability. The slope compensation is 900mV/Ts,
which changes with frequency. The gain for the current sensing
circuit is typically 300mV/A. The control reference for the current
loops comes from the error amplifier's (EAMP) output.
The PWM operation is initialized by the clock from the oscillator.
The P-channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp-up. When the
sum of the current amplifier CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
P-FET and turn on the N-Channel MOSFET. The N-FET stays on until
the end of the PWM cycle. Figure 26 shows the typical operating
waveforms during the PWM operation. The dotted lines illustrate
the sum of the slope compensation ramp and the current-sense
amplifier’s CSA output.
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
FIGURE 26. PWM OPERATION WAVEFORMS
The reference voltage is 0.6V, which is used by Feedback to
adjust the output of the error amplifier, VEAMP. The error
amplifier is a trans conductance amplifier that converts the
voltage error signal to a current output. The voltage loop is
internally compensated with the 27pF and 200kΩ RC network.
The maximum EAMP voltage output is precisely clamped to 1.6V.
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in the “Functional
Block Diagram” on page 4. The current sensing circuit has a gain
of 300mV/A, from the P-FET current to the CSA output. When the
CSA output reaches a threshold, the OCP comparator is tripped to
turn off the P-FET immediately. The overcurrent function protects
the switching converter from a shorted output by monitoring the
current flowing through the upper MOSFET.
Upon detection of overcurrent condition, the upper MOSFET will
be immediately turned off and will not be turned on again until
the next switching cycle. If the overcurrent condition goes away,
the output will resume back into regulation point.
Short-Circuit Protection
The short-circuit protection (SCP) comparator monitors the VFB
pin voltage for output short-circuit protection. When the VFB is
lower than 0.3V, the SCP comparator forces the PWM oscillator
frequency to drop to 1/3 of the normal operation value. This
comparator is effective during start-up or an output short-circuit
event.
Negative Current Protection
Similar to the overcurrent, the negative current protection is
realized by monitoring the current across the low-side N-FET, as
shown in the “Functional Block Diagram” on page 4. When the
valley point of the inductor current reaches -1.5A for 2 consecutive
cycles, both P-FET and N-FET shut off. The 100Ω in parallel to the
N-FET will activate discharging the output into regulation. The
control will begin to switch when output is within regulation.
PG
PG is an output of a window comparator that continuously monitors
the buck regulator output voltage. PG is actively held low when EN is
low and during the buck regulator soft-start period. After 1ms delay
of the soft-start period, PG becomes high impedance as-long-as the
output voltage is within nominal regulation voltage set by VFB.
When VFB drops 15% below or raises 15% above the nominal
regulation voltage, the device pulls PG low. Any fault condition forces
PG low until the fault condition is cleared by attempts to soft-start.
There is an internal 5MΩ pull-up resistor to fit most applications. An
external resistor can be added from PG to VIN for more pull-up
strength.
UVLO
When the input voltage is below the undervoltage lock-out (UVLO)
threshold, the regulator is disabled.
Enable, Disable and Soft Start-up
After the VIN pin exceeds its rising POR trip point (nominal 2.7V),
the device begins operation. If the EN pin is held low externally,
nothing happens until this pin is released. Once the EN is
released and above the logic threshold, the internal default
soft-start time is 1ms.
Discharge Mode (Soft-stop)
When a transition to shutdown mode occurs or the VIN UVLO is set,
the outputs discharge to GND through an internal 100Ω switch.
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