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BD1482EFJ Schematic ( PDF Datasheet ) - ROHM Semiconductor

Teilenummer BD1482EFJ
Beschreibung Synchronous Buck Converter integrated FET
Hersteller ROHM Semiconductor
Logo ROHM Semiconductor Logo 




Gesamt 20 Seiten
BD1482EFJ Datasheet, Funktion
Datasheet
4.2V to 18V, 2A 1ch
Synchronous Buck Converter integrated FET
BD1482EFJ
General Description
The BD1482EFJ is a synchronous step-down
switching regulator that integrates 2 low ON-resistance
N-channel MOSFETs. It achieves 2A continuous
output current over a wide input supply range. Current
mode operation provides fast transient response and
easy phase compensation.
Features
Low ESR Output Ceramic Capacitors are
Available
Low Standby Current during Shutdown Mode
380 kHz Fixed Operating Frequency
Feedback voltage
0.923V ± 1.5%(Ta=25),
0.923V ± 2.0%(Ta=-25to 85)
Protection Circuits
Under Voltage Lockout Protection
Thermal Shutdown
Over Current Protection
Key Specifications
Input voltage range:
4.2V to 18V
Output voltage range:
0.923V to (Vin×0.7)V
Output current:
2.0A (Max.)
Switching Frequency
380kHz(Typ.)
Hi-side FET On-resistance:
0.15Ω(Typ.)
Lo-side FET On-resistance:
0.13Ω(Typ.)
Standby current:
15μA (Typ.)
Operating temperature range:
-40to +85
Package
HTSOP-J8
(Typ.) (Typ.) (Max.)
4.90mm x 6.00mm x 1.00mm
Applications
Distributed Power System
Pre-Regulator for Linear Regulator
Typical Application Circuit
C_SS
0.1μF
HTSOP-J8
C_PC
3300pF
R_PC
7.5kΩ
R_DW
15kΩ
R_UP
39kΩ
Thermal Pad
(to be shorted to GND)
VIN 12V
C_VC1
10μF
L
10µH
VOUT 3.3V
C_CO1
20μF
R_BS protect from VIN-BST short destruction.
Fig.1 Typical Application Circuit
Product structureSilicon monolithic integrated circuit
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ2211114001
This product is not designed protection against radioactive rays.
TSZ02201-0333AD100130-1-2
1/17 06.Aug.2012 Rev.001






BD1482EFJ Datasheet, Funktion
BD1482EFJ
Typical Performance Curves
(Unless otherwise specified, VIN= 12V Ta = 25) (Continued)
Datasheet
Fig.12 Soft Start Time
VOUT
VOUT-MIN: -43.5mV
VOUT-MAX: +37.5mV
VOUT: 50mV/div
IOUT
IOUT: 1.0A/div
500usec/div
Fig.13 Transient Response
(VIN= 12V VOUT= 3.3V L= 10µH Cout =22µF Iout= 0.2-1.0A )
VOUT
: +22.8mV
VOUT: 20mV/div
VOUT
IOUT
VOUT-MAX: +87mV
VOUT-MIN: -98mV
VOUT: 100mV/div
IOUT: 1.0A/div
500usec/div
Fig.14 Output Ripple Voltage
(VIN= 12V VOUT= 3.3V L= 10µH Cout =22µF Iout= 1.0A )
Fig.15 Transient Response
(VIN= 12V VOUT= 3.3V L= 10µH Cout =22µF Iout= 0.2-2.0A)
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
6/17
TSZ02201-0333AD100130-1-2
06.Aug.2012 Rev.001

6 Page









BD1482EFJ pdf, datenblatt
BD1482EFJ
Datasheet
Layout Pattern Consideration
Two high pulsing current flowing loops exist in the buck regulator system. The first loop, when FET is ON, starts from the
input capacitors, to the VIN terminal, to the SW terminal, to the inductor, to the output capacitors, and then returns to the
input capacitor through GND. The second loop, when FET is OFF, starts from the low FET, to the inductor, to the output
capacitor, and then returns to the low FET through GND. To reduce the noise and improve the efficiency, please minimize
these two loop area. Especially input capacitor, output capacitor and low FET should be connected to GND plain.
PCB Layout may affect the thermal performance, noise and efficiency greatly. So please take extra care when designing
PCB Layout patterns.
VIN
CIN
FET
L
VOUT
COUT
Fig.26 Current loop in Buck regulator system
The thermal Pad on the back side of IC has the great thermal conduction to the chip. So using the GND plain as broad and
wide as possible can help thermal dissipation. And a lot of thermal via for helping the spread of heat to the different layer
is also effective.
The input capacitors should be connected as close as possible to the VIN terminal.
When there is unused area on PCB, please arrange the copper foil plain of DC nodes, such as GND, VIN and VOUT for
helping heat dissipation of IC or circumference parts.
To avoid the noise influence from AC combination with the other line, keep the switching line such as SW not extend as
much as possible, and trace shortly and thickly to coil.
Keep sensitive signal traces such as trace connected FB and COMP away from SW pin.
The inductor and the output capacitors should be placed close to SW pin as much as possible.
CIN
BST
VIN EN
SW
GND
L COUT
VOUT
Fig.27 The example of PCB layout pattern
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
12/17
TSZ02201-0333AD100130-1-2
06.Aug.2012 Rev.001

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