Datenblatt-pdf.com


VT6130 Schematic ( PDF Datasheet ) - VIA

Teilenummer VT6130
Beschreibung PCI Express Gigabit Ethernet Controller
Hersteller VIA
Logo VIA Logo 




Gesamt 30 Seiten
VT6130 Datasheet, Funktion
Data Sheet
VT6130
PCI Express Gigabit
Ethernet Controller
with
ACPI and Management Functions
(Released under Creative Commons License)
Preliminary Revision 1.0
November 28, 2008
VIA TECHNOLOGIES, INC.






VT6130 Datasheet, Funktion
VT6130 Data Sheet
VT6130
Gigabit Ethernet Controller for PCI Express
PRODUCT FEATURES
Key Features
– Fully IEEE 802.3, 802.3u (10BASE-T, 100BASE-TX), 802.3ab (1000BASE-T) & 802.3z (1000BASE-X) compliant
– Supports half / full duplex mode and 802.3x Flow Control
– 2 build-in linear regulator to generate 2.1 and 1.2 Voltage
– Automatic detection & correction of cable pair swaps, pair skew, & pair polarity, along with an Auto MDI/MDI-X
crossover function
– Built-in integrated oscillator circuit
– Four direct drive LED pins with programmable LED modes
– Low EMI line drivers with robust CESD performance
Bus Architecture
– Compliance to PCI Express Rev1.1
– Supports Advanced Error Reporting capability
– Active State Power Management (ASPM) to L0s and L1
– PCIe Bus master Dual Channel DMA support for Tx/Rx
– Tx/Rx descriptor Scatter and Gather support in host memory
– No Transmit data byte alignment restriction, Rx data buffer should be double word alignment
– Flexible programmable max read request sizes and advanced internal arbitration control to optimize the bus
utilization
– 256 bytes IO map/ 256 bytes memory map IO range in 32-bit/64-bit addressing
– 64-bit addressing Option in slave mode is loading from EEPROM
– Bus Slave support 64-bit addressing
– Use global Descriptor DMA and FIFO DMA Hi-16 bit address
– Adaptive interrupt service scheme for interrupt Coalescence
Network Functionality
– 64 x 48 CAM for 32 perfect filtering & 32 interest packet perfect filtering
– Supports jumbo frames up to 8KB
– Integrates on-chip TX and RX FIFO for high performance application
Network Management
– WFM2.0 enable for server
– SNMP-management, DMI2.0, PXE2.1
– Advanced Configuration Power management Interface (ACPI), Wake On Lan and Microsoft onNow
– Supports PCI Message Signaled Interrupt (MSI)
– PCI PMU1.1
– 802.1Q VLAN, 64x12 CAM VLAN ID perfect filtering
– Long frame support (1518 + 4)
– VLAN tag insertion for transmit packets
– VLAN tag detection and removal for receive packets.
Preliminary Revision 1.0, November 28, 2008
-1-
Product Features

6 Page









VT6130 pdf, datenblatt
VT6130 Data Sheet
Signal Name
SPICSB#
SPIDI / EDI
SPIDO / EDO
SPISK / ESK
Pin #
23
27
26
28
Signal Name
MDI0P,
MDI0M
MDI1P,
MDI1M
MDI2P,
MDI2M
MDI3P,
MDI3M
Pin #
50, 51
53, 54
58, 59
61, 62
Signal Name
LED0
LED1
LED2
LED3
Pin #
41
42
43
44
Signal Name
WAKE#
Pin #
18
Signal Name
X1
Pin #
47
X2 46
SPI Flash Interface
I/O Signal Description
O SPI Flash Chip Select. Chip select signal of the external SPI Flash.
O SPI Flash Data In. External SPI Flash data input.
I SPI Flash Data Out. External SPI Flash data output.
O SPI Clock. External SPI Flash clock
Media Interface
I/O Signal Description
I/O Twisted-Pair Media Dependent Interface.
In 1000BASE-T mode, all 4 pairs are both input and output at the same time.
In 100BASE-TX and 10BASE_T modes:
MDI0P/MDI0M are used for transmit pair under MDI configuration and for
receive pair under MDIX configuration.
MDI1P/MDI1M are used for receive pair under MDI configuration and for
transmit pair under MDIX configuration.
In 100BASE-TX and 10BASE-T modes:
MDI2P/MDI2M and MDI3P/MDI3M are unused.
LED Status Output
I/O Signal Description
O LED Status Outputs. Output pins for directly driving status LEDs.
When enabled by SMI register bit 27.3, all LED outputs are pulsed at 5kHz
with a 20% duty cycle for low-power operation.
Power Management Interface
I/O Signal Description
OD System WakeUp. This signal is asserted low to reactivate the PCI Express
slot’s main power rails and reference clocks.
System Clock Interface
I/O Signal Description
I Crystal Input. The reference input clock is 25MHz, with a +50ppm frequency
tolerance or connected to a 25MHz, parallel resonant crystal with a +50ppm
frequency tolerance. When used with a crystal, a 33pF capacitor is connected
from this pin to ground.
O Crystal Output. 25MHz parallel resonant crystal output. A 33pF capacitor is
connected from this output to ground.
Preliminary Revision 1.0, November 28, 2008
-7-
Pin Descriptions

12 Page





SeitenGesamt 30 Seiten
PDF Download[ VT6130 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
VT6130PCI Express Gigabit Ethernet ControllerVIA
VIA

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche