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Número de pieza | XS1-L02A-QF124 | |
Descripción | Dual-Tile Multicore Microcontroller | |
Fabricantes | Xmos | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de XS1-L02A-QF124 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
No Preview Available ! XS1-L02A-QF124 Datasheet
2012/10/12
XMOS © 2012, All Rights Reserved
Document Number: X1189,
1 page XS1-L02A-QF124 Datasheet
3 Signal Description
4
Module
Power
PLL
JTAG
PCU
Tile 0 I/O
X1189,
Signal
Function
Type
Active Properties
PU=Pull Up, PD=Pull Down, ST=Schmitt Trigger Input, OT=Output Tristate, S=Switchable
GND
RS=Required for SPI boot (§5.6), RU=Required for USB-enabled devices (§10)
Digital ground
GND
—
VDD
Digital tile power
PWR
—
VDDIO
Digital I/O power
PWR
—
PLL_AGND
Analog ground for PLL
PWR
—
PLL_AVDD
Analog PLL power
PWR
—
PCU_VDD
PCU tile power
PWR
—
PCU_VDDIO
PCU I/O supply
PWR
—
OTP_VCC
OTP power supply
PWR
—
RST_N
Global reset input
Input
Low
CLK PLL reference clock
Input
—
PD, ST
MODE[4:0]
Boot mode select
Input
—
PU, ST
TDI Test data input
Input
—
PU, ST
TDO
Test data output
Output —
PD, OT
TMS
Test mode select
Input
—
PU, ST
TRST_N
Test reset input
Input
Low
TCK
Test clock
Input
—
PU, ST
DEBUG_N
Multi-chip debug
I/O
Low
PU
PCU_WAKE
Wakeup reset
Input
—
PD, ST
PCU_GATE
Power control gate control
Output —
OT
PCU_CLK
Clock input
Input
—
PD, ST
X0D00
X0D01
X0D02
X0D03
X0D04
X0D05
X0D06
X0D07
X0D08
X0D09
X0D10
X0D11
X0D12
X0D13
X0D14
X0D15
X0D16
X0D17
P1A0
XLA45ob P1B0
XLA35ob
P4A0 P8A0 P16A0
XLA25ob
P4A1 P8A1 P16A1
XLA12bo/5b
P4B0 P8A2 P16A2
XLA02bo/5b
P4B1 P8A3 P16A3
XLA02bi /5b
P4B2 P8A4 P16A4
XLA12bi /5b
P4B3 P8A5 P16A5
XLA25ib
P4A2 P8A6 P16A6
XLA35ib
P4A3 P8A7 P16A7
XLA45ib P1C0
P1D0
P32A20
P32A21
P32A22
P32A23
P32A24
P32A25
P32A26
P32A27
P1E0
XLB45ob
P1F0
XLB35ob
P4C0 P8B0 P16A8 P32A28
XLB25ob
P4C1 P8B1 P16A9 P32A29
XLB12bo/5b
P4D0 P8B2 P16A10
XLB02bo/5b
P4D1 P8B3 P16A11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PDS, RS
PDS, RS
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RS
PDS, RS
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
(continued)
5 Page XS1-L02A-QF124 Datasheet
10
Figure 2:
PLL multiplier
values and
MODE pins
Oscillator
Frequency
5-13 MHz
13-20 MHz
20-48 MHz
48-100 MHz
MODE
10
00
11
10
01
Tile
Frequency
130-399.75 MHz
260-400.00 MHz
167-400.00 MHz
196-400.00 MHz
PLL Ratio
30.75
20
8.33
4
PLL settings
OD F R
1 122 0
2 119 0
2 49 0
2 23 0
OD, F and R must be chosen so that 0 ≤ R ≤ 63, 0 ≤ F ≤ 4095, 0 ≤ OD ≤ 7, and
2b6y0wMriHtinzg≤toFotshce×dFig+2i1ta×l nRo+1d1e≤P1LL.3cGoHnfizg. uTrhaetiOonDr,eFg,isatnedr. R values can be modified
The MODE pins must be held at a static value until the third rising edge of the
system clock following the deassertion of the system reset.
For 500 MHz parts, once booted, the PLL must be reprogrammed to provide this
tile frequency. The XMOS tools perform this operation by default.
Further details on configuring the clock can be found in the XS1-L Clock Frequency
Control document, X1433.
5.6 Boot ROM
The xCORE Tile boot procedure is illustrated in Figure 3. In normal usage,
MODE[4:2] controls the boot source according to the table in Figure 4. If bit
5 of the security register (see §5.7.1) is set, the device boots from OTP.
Start
Boot ROM
Primary boot
Security Register
Figure 3:
Boot
procedure
OTP
Bit [5] set
No
Yes
Copy OTP contents
to base of SRAM
Boot according to
boot source pins
Execute program
X1189,
11 Page |
Páginas | Total 25 Páginas | |
PDF Descargar | [ Datasheet XS1-L02A-QF124.PDF ] |
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