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PDF ADC12QS065 Data sheet ( Hoja de datos )

Número de pieza ADC12QS065
Descripción Quad 12-Bit 65 MSPS A/D Converter
Fabricantes National Semiconductor 
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No Preview Available ! ADC12QS065 Hoja de datos, Descripción, Manual

PRELIMINARY
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ADC12QS065
Quad 12-Bit 65 MSPS A/D Converter with LVDS
Serialized Outputs
General Description
This is Preliminary Information for a product currently in
development. ALL specifications are design targets and
are subject to change.
The ADC12QS065 is a low power, high performance CMOS
4-channel analog-to-digital converter with LVDS serialized
outputs. The ADC12QS065 digitizes signals to 12 bits reso-
lution at sampling rates up to 65 MSPS while consuming a
typical 200 mW/ADC from a single 3.0V supply. Sampled
data is transformed into high speed serial LVDS output data
streams. Clock and frame LVDS pairs aid in data capture.
The ADC12QS065’s six differential pairs transmit data over
backplanes or cable and also make PCB design easier. In
addition, the reduced cable, PCB trace count, and connector
size tremendously reduce cost.
No missing codes performance is guaranteed over the full
operating temperature range. The pipeline ADC architecture
achieves >11 Effective Bits over the entire Nyquist band at
65 MSPS.
The ADC12QS065 output pins can be put into a high imped-
ance state. The serializer PLL can lock to frequencies be-
tween 20 MHz and 65 MHz.
When not converting, power consumption can be reduced by
pulling the PD (Power Down) pin high, placing the converter
into a low power state where it typically consumes less than
3 mW total, and from which recovery is less than 5 ms. The
ADC12QS065’s speed, resolution and single supply opera-
tion makes it well suited for a variety of applications in
ultrasound, imaging, video and communications. Operating
over the industrial (-40˚C to +85˚C) temperature range, the
ADC12QS065 is available in a 64 pin TQFP package.
Features
n Single +3.0V supply operation
n Internal sample-and-hold
n Internal reference
n Low power consumption
n Power down mode
n Clock and Data Frame Timing
n 780 Mbps serial LVDS data rate (at 65 MHz clock)
n LVDS serial output rated for 100 Ohm load
Key Specifications
n Resolution
n DNL
n SNR (fIN = 10 MHz)
n SFDR (fIN = 10 MHz)
n ENOB (at Nyquist)
n Power Consumption
n -- Operating, 65 MSPS, per ADC
n -- Power Down Mode
12 Bits
±0.3 LSB (typ)
68.5 dB (typ)
85 dB (typ)
11 Bits (typ)
200 mW (typ)
< 3 mW (typ)
Applications
n Ultrasound
n Medical Imaging
n Communications
n Portable Instrumentation
n Digital Video
Connection Diagram
© 2005 National Semiconductor Corporation DS201068
20106801
www.national.com

1 page




ADC12QS065 pdf
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VA, VD, VDR
|VA–VD|
Voltage on any pin to GND (valid for
pins 1-30 and 51-64)
3.8V
100 mV
−0.3V to (VA or VD
+0.3V)
Voltage on any Pin to GND (valid
-0.3V to 2.2V
for pins 31-50)
Input Current at Any Pin (Note 3)
±25 mA
Package Input Current (Note 3)
±50 mA
Package Dissipation at TA = 25˚C
LVDS Output Short Circuit Duration
See (Note 4)
10 ms
ESD Susceptibility
Human Body Model (Note 5)
2500V
Machine Model (Note 5)
250V
Soldering Temperature,
Infrared, 10 sec. (Note 6)
235˚C
Storage Temperature
−65˚C to +150˚C
Operating Ratings (Notes 1, 2)
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Operating Temperature
−40˚C TA +85˚C
Supply Voltage (VA, VD, VDR)
VIN Differential Input Range
VCM Input Common Mode
Range (Differential Input)
+2.7V to +3.6V
±VREF
VREF/2 to (VA - VREF/2 )
VREF Voltage Range
0.5V to 1.0V
Digital Input Pins Voltage
Range (excludes pins 31 to
−0.3V to (VA + 0.3V)
50)
|AGND–DGND|
100mV
Clock Duty Cycle
30% to 70%
Converter Electrical Characteristics
NOTE: This product is currently under development. As such, the parameters specified in this section are DESIGN
TARGETS. The specifications in this section cannot be guaranteed until device characterization has taken place. Un-
less otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = VDR= +3.0V, VIN =
2VP-P , VREF = +1.0V external, VCOM=1.5V, fCLK = 65 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply
for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical Limits
(Note 10) (Note 10)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
12 Bits (min)
INL Integral Non Linearity (Note 11)
±0.6
LSB (max)
DNL
Differential Non Linearity
±0.3
LSB (max)
GE Positive Gain Error
±0.5
%FS (max)
NGE
Negative Gain Error
±0.5
%FS (max)
TC GE
VOFF
Gain Error Tempco
Offset Error (VIN+ = VIN−)
−40˚C TA +85˚C
5
±0.15
ppm/˚C
%FS (max)
%FS (min)
TC
VOFF
Offset Error Tempco
Under Range Output Code
−40˚C TA +85˚C
4 ppm/˚C
00
Over Range Output Code
4095
4095
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VCM Common Mode Input Voltage
0.5 V (min)
1.5
2.0 V (max)
VIN Analog Differential Input Range
CIN
VIN Input Capacitance (each pin to
GND)
VIN = 2.5 Vdc
+ 0.7 Vrms
(CLK LOW)
(CLK HIGH)
8
3
2.0
VP-P
pF
pF
VREF
External Reference Voltage (Note
13)
1.00
0.8
1.2
V (min)
V (max)
IREF Reference Input Current
TCVCMO Reference Temperature Coefficient
<1 µA
80 ppm/˚C
5 www.national.com

5 Page





ADC12QS065 arduino
Timing Diagram
www.DataSheet4U.com
Transfer Characteristic
LVDS Output Timing
20106809
FIGURE 1. Transfer Characteristic
11
20106810
www.national.com

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