LC7872E Schematic ( PDF Datasheet ) - Sanyo Semicon Device

Teilenummer LC7872E
Beschreibung CD Graphics Decoder
Hersteller Sanyo Semicon Device
Logo Sanyo Semicon Device Logo 

Gesamt 17 Seiten
LC7872E Datasheet, Funktion
Ordering number : EN4868A
CD Graphics Decoder
The LC7872E is a CMOS LSI that integrates in a single
chip the signal processing functions required for compact
disk graphics (CD-G) decoding. The LC7872E accepts the
subcode R to W signals output by a CD-DSP chip such as
the Sanyo LC786X series, LC7862XE series or
LC7863XE series and performs de-interleaving, error
detection and correction, graphics instruction processing
and image processing.
• Built-in RGB encoder allows a CD-G decoder to be
implemented in just two chips: the LC7872E and an
external 64-kword × 4-bit DRAM
• Interpolation and protection for the CD subcode
synchronization signals as well as de-interleaving, error
detection and correction for the R to W signals.
• Two crystal oscillator systems, one for NTSC and one
for PAL are provided and can be switched easily using
the control pin provided. The standard clock and all
required internal timings can be generated by
connecting a 14.31818 MHz crystal for NTSC and/or a
17.734476 MHz crystal for PAL.
• The LC7872E performs CD graphics instruction
processing and drawing processing and controls the
image display.
• Composition video 8-bit D/A converter output provided
• Superimposition support
• Microprocessor interface provided to support set
• Define transparency support
• Color bar output function
• A CD-G decoder can be implemented with just two
chips: a controller is not required.
• Silicon gate CMOS structure for low power operation
• Single 5 V power supply
• 64-pin QFP (QIP) package
Package Dimensions
unit: mm
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
O3097HA (OT)/20695TH (OT) No. 4868-1/17

LC7872E Datasheet, Funktion
A0 to A7
DB0 to DB3
Figure 3 DRAM Early Write Cycle
A0 to A7
DB0 to DB3
Figure 4 DRAM Page Mode Read Cycle
No. 4868-6/17

6 Page

LC7872E pdf, datenblatt
• LC7861N/67 interface (Pin names in parentheses are DSP pins.)
• LC7868/69/681 interface
Identical to the LC7861N/67 interface except that the SBCK polarity is reversed (the shift occurs on the rising
3. DRAM Interface; A0 to A7, DB0 to DB3, RAS, CAS, WE, OE
The LC7872E uses an external 64-kword × 4-bit DRAM.
4. Display Format; DEN, N/P1, N/P2, CSYNC, VRESET, HRESET, YS, VIDEO, PALID and TRANS0 to TRANS5
• Data to which error detection and correction has been applied is encoded by the RGB encoder and the 8-bit D/A
converter output is output from the VIDEO pin. This circuit handles both NTSC and PAL formats and either mode
can be specified using the N/P pins. See item 1 for details on the pin states for the NTSC and PAL specifications.
• The 4FSC2, FSCIN, YS, VRESET, HRESET, PALID and TRANS0 to TRANS5 pins are used in superimposition
mode. The image may be disrupted if the VRESET and HRESET signals are not synchronized with 4FSC2.
The PALID pin is controlled in PAL mode, and is used to match the LC7872E burst signal to the burst component
of the external video signal. When this pin is high, the phase of the burst signal changes every horizontal period,
and when this pin is low, the phase does not change.
The YS pin outputs a control signal used to switch between an external video signal and the LC7872E video signal.
The output conditions for this signal are set by the 2N byte command input registers 0, E, F, and G. The pins
TRANS0 through TRANS5 output signals according to the define transparency instruction.
• The DEN pin is a display control pin. The internal font data is output when DEN is low and the color data set up in
the registers is used when DEN is high. The default state is blue.
No. 4868-12/17

12 Page

SeitenGesamt 17 Seiten
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