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LC78711 Schematic ( PDF Datasheet ) - Sanyo Semicon Device

Teilenummer LC78711
Beschreibung Graphics Display Processor
Hersteller Sanyo Semicon Device
Logo Sanyo Semicon Device Logo 




Gesamt 30 Seiten
LC78711 Datasheet, Funktion
Ordering number : EN5476
CMOS LSI
LC78711E
Graphics Display Processor
Overview
The LC78711E is a CMOS LSI that provides graphics
display drawing functions. In addition to implementing
graphics display for NTSC and PAL signals, it provides
two 32 × 32-dot sprite display patterns and can easily
implement a wide range of displays.
Features
• Two-chip structure consisting of this LSI, the
LC78711E, and an external 64-K × 4-bit RAM. (An
RGB encoder is built in.)
• Graphics drawing controlled by a microprocessor over a
serial interface.
• Includes two crystal oscillator systems, one for NTSC
and one for PAL, and these system can be easily
switched using the provided control pin.
The standard clocks and all necessary internal timings
can be generated by connecting two crystals, a
14.31818-MHz crystal for NTSC, and a 17.734476-MHz
crystal for PAL.
• Two 32 × 32-dot sprite patterns provided. Up to two
sprites can be displayed, either two different types or the
same pattern in two different locations.
• 16 colors from a palette of 4096 colors can be displayed
in graphics screens, and seven colors can be displayed in
sprite patterns.
• Y/C signal outputs (two 8-bit D/A converter outputs)
• Supports the superimpose function, and provides a
timing signal output.
• Provides a color bar signal output function.
• Adopts an 8-bit serial data input format for the external
control input.
Package Dimensions
unit: mm
3159-QFP64E
[LC78711E]
SANYO: QFP64E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
63096HA (OT) No. 5476-1/43






LC78711 Datasheet, Funktion
LC78711E
Continued from preceding page.
Pin no.
51
52
53
Pin
TEST12
PALID
HRESET
Pin type
Test input
PAL mode external control input
External horizontal
synchronization input
54
FSCO
Clock output
External vertical
55
VRESET
synchronization input
56 INIT Initialization input
57
RESET
Reset input
58
N/P1
NTSC/PAL selection
59
N/P2
NTSC/PAL selection
60
SON
Superimpose control
61
XIN2
Crystal oscillator element
62
XOUT2
connections
63
XIN1
Crystal oscillator element
64
XOUT1
connections
I/O Polarity
Pin function
I Positive Test input. Must be connected to ground during normal operation.
External superimpose function control input for PAL mode
I Positive (A pull-up resistor is built in.)
I Negative External horizontal synchronization timing control input
Subcarrier clock output
O Positive NTSC mode: 3.579545 MHz
PAL mode: 4.433619 MHz
I Negative External vertical synchronization timing control input
I Negative System initialization signal input
I Negative System reset signal input
NTSC/PAL selection input (RGB encoder block)
I Positive High: NTSC, low: PAL
NTSC/PAL selection input (decoder block)
I Positive High: NTSC, low: PAL
Superimpose function on/off control input
I Positive High: superimpose on
I — Connections for the PAL crystal oscillator element
O — (4·fsc = 17.734476 MHz)
I — Connections for the NTSC crystal oscillator element
O — (4·fsc = 14.31818 MHz)
Timing Characteristics (DRAM access timing) at Ta = +25°C, DVDD1 = 5 V
Parameter
Random read/write cycle
Page mode cycle
RAS access time
CAS access time
Output turn off delay
RAS precharge time
RAS pulse width
RAS pulse width (page mode)
RAS hold time
CAS hold time
CAS pulse width
CAS precharge time
CAS precharge time
Row address setup time
Row address hold time
Column address setup time
Column address hold time
Read command setup time
Read command hold time
Read command hold time
Write command setup time
Write command hold time
Write command pulse width
Write data setup time
Write data setup time
CAS setup time
CAS hold time
RAS precharge CAS active time
Refresh time
Symbol
Conditions
tRC
tPC
tRAC
tCAC
tOFF
tRP
tRAS
tRASP
tRSH
tCSH
tCAS
tCPN
tCP
tASR
tRAH
tASC
tCAH
tRCS
tRCH
tRRH
tWCS
tWCH
tWP
tDS
tDH
tCSR
tCHR
tRPC
tREF
Page mode
Referenced to CAS
Referenced to RAS
CAS before RAS
CAS before RAS
min
250
130
100
120
60
120
60
50
50
100
50
0
50
150
120
120
100
50
150
100
100
50
50
50
Ratings
typ
max
210
10
20
18000
3.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
No. 5476-6/43

6 Page









LC78711 pdf, datenblatt
LC78711E
Function Overview
1. Crystal clock oscillator; XIN1, XOUT1, XIN2, XOUT2, N/P1, N/P2, FSCO
The XIN1 and XOUT1 pins are connections for an NTSC 14.31818-MHz crystal element, and the XIN2 and XOUT2
pins are connections for a PAL 17.734476-MHz crystal element. The N/P1 pin switches the LC78711E RGB encoder
block between NTSC and PAL modes, and the N/P2 pin switches the decoder block between NTSC and PAL modes.
The FSCO pin outputs a clock signal that is the crystal oscillator frequency divided by 4. The table below enumerates
the pin states vs. the LC78711E operating modes.
XIN1, XOUT1
14.31818 MHz
*
14.30244 MHz
XIN2, XOUT2
*
17.734476 MHz
*
N/P1
H
L
L
N/P2
H
L
H
TV format
NTSC/M
PAL/GBIDH
PAL/M
FSCO
3.579545 MHz
4.433619 MHz
3.575611 MHz
2. Display format; N/P1, N/P2, LINE, CSYNC, SON, 4FSC2, FSCIN, VRESET, HRESET, YS, PALID
• The LC78711E supports both NTSC and PAL modes, with the N/P1 and N/P2 pins being used to set the mode. See
item (1) above for the pin states in the NTSC and PAL modes. The LINE pin switches the number of scan lines in a
1-V period.
• The SON, 4FSC2, FSCIN, VRESET, HRESET, YS, and PALID pins are used with the superimpose function. The
4FSC2 pin inputs a 4 × fsc frequency, and the FSCIN pin inputs the fsc frequency. The VRESET and HRESET
pins input the external video signal VSYNC and HSYNC. The internal V and H counters are reset on the falling
edges of these signals, respectively. The image may be disrupted if the 4FSC2 signal is not locked with the
VRESET and HRESET signals. The YS pin is used to switch the video signal. The PALID pin is used for burst
waveform phase matching in PAL mode.
3. DRAM interface
Interface pins: A0 to A7, DB0 to DB3, RAS, CAS, WE, OE
An external 64k × 4-bit DRAM must be used.
4. Video outputs: VIDEO1, VIDEO2
The luminance signal can be acquired from the VIDEO1 pin.
The chrominance signal can be acquired from the VIDEO2 pin.
No. 5476-12/43

12 Page





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