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LC78601E Schematic ( PDF Datasheet ) - Sanyo Semicon Device

Teilenummer LC78601E
Beschreibung Compact Disc Player DSP with Built-in Microcontroller
Hersteller Sanyo Semicon Device
Logo Sanyo Semicon Device Logo 




Gesamt 11 Seiten
LC78601E Datasheet, Funktion
Ordering number : EN6020
CMOS IC
LC78601E
Compact Disc Player DSP with
Built-in Microcontroller
Overview
The LC78601E CMOS IC implements compact disc
player signal processing, servo control, LCD display, key
input acquisition, and remote controller processing
without requiring control by a separate microcontroller.
The basic functions provided include demodulation of the
EFM signal from the optical pickup, deinterleaving, error
detection and correction, 8× oversampling digital filters,
D/A converter (with built-in analog low-pass filter), LCD
driver, remote controller processing, key acquisition, and
control processing. Thus this IC can provide excellent
cost/performance characteristics when implementing a
low-end CD player.
Functions
• Implements CD play/pause, disc stop, track selection,
fast forward, reverse, repeat mode playback of 1 track or
the whole disc, programmed play (setup, play, and clear)
of up to 16 tracks, and random repeat play under the
control of key input or remote controller input.
<Signal-Processing Block>
• Slices an input high-frequency signal at an accurate
level, converts the EFM signal, and generates a clock
with an average frequency of 4.3218 MHz using a PLL
circuit that performs a phase comparison with an
internal VCO.
• Accurately generates not only the reference clock but
also all necessary internal timings using an external
16.9344MHz crystal.
• Controls the disc motor speed using a frame difference
signal created based on the reproduced clock signal and
a reference clock.
• Performs detection, protection, and interpolation for the
frame synchronizing signal to assure stable data readout.
• Demodulates the EFM signal, converting it to 8-bit
symbol data.
• Separates the subcode data from the EFM signal and
outputs that data to the internal control processing block.
• After applying a CRC check to the subcode Q signal,
outputs that signal to the internal control processing
block.
• Buffers the demodulated EFM signal data in internal
RAM and compensates for ±4 frames of jitter due to
disc speed fluctuations.
• Performs unscrambling and deinterleaving by reordering
the demodulated EFM signal data to the stipulated order.
• Performs error detection and correction and flag
processing (C1: dual errors, C2: dual errors)
• The C2 flags are set based on the C1 flags and the result
of the C2 processing, and the signal is interpolated or
previous value hold is applied based on the C2 flags.
Dual interpolation is adopted in the interpolation circuit.
Previous value hold is applied if two or more
consecutive errors are indicated by the C2 flags.
• Performs track jump, focus start, disc motor start/stop,
muting on/off, track count, and other operations under
control of the internal control processing block.
• Provides digital outputs.
• Generates D/A converter input signals with continuity
improved by 8× oversampling digital filters.
• Includes on-chip third-order noise shaper delta-sigma
D/A converters with built-in analog low-pass filter.
• Digital deemphasis circuit
• Adopts zero-cross muting.
<Display Block>
• On-chip LCD drivers for 2-digit display plus play,
program, repeat, and random indicators
• On-chip bias voltage generator
<Control Processing Block>
• Key matrix circuit with 4 inputs and 2 outputs for an
8-key matrix
• Supports remote controller input.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D1898RM (OT) No. 6020-1/11






LC78601E Datasheet, Funktion
LC78601E
Pin Functions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Pin
DEFI
3 V/*5 V
PDO
VVSS
ISET
VVDD
FR
VSS
EFMO
EFMIN
TMOD
CLV
HFL
TES
TOFF
TGL
JP
LASER
FSTA
EFBAL
SP8
VDD
FSEQ
24 PCK
25 SLOF
26 SLED+
27 SLED–
28 PUIN
29 DOUT
30 S6
31 S5
32 S4
33 S3
34 S2
35 S1
36 COM3
37 COM2
38 COM1
39 VSS
40 VLCD1
41 *KEYI4
42 *KEYI3
43 *KEYI2
44 *KEYI1
45 *KEYO1
46 *KEYO2
47 *RANDOM
48 RMTSL3
I/O
Function
Pin state during reset
I Defect detection signal (DEF) input. (Must be connected to 0 V if unused.)
I Supply voltage selection input. (High: 3V operation, low: 5V operation)
O Internal VCO control phase comparator output
Undefined
— Internal VCO ground. This pin must be connected to 0 V.
AI PLL circuit pins PDO output current adjustment resistor connection
— Internal VCO power supply
AI VCO frequency range adjustment
— Digital system ground. This pin must be connected to 0 V.
O Slice level
I control pins
EFM signal output
EFM signal input
Undefined
I Test input. This pin must be connected to 0 V.
O Disc motor control output. This is a 3-value output.
Hi-Z
I Track detection signal input. This is a Schmitt input.
I Tracking error signal input. This is a Schmitt input.
O Tracking off output
High output
O Tracking gain switching output. A low level output raises the gain.
Undefined
O Track jump control output. This is a 3-value output.
Hi-Z
O Laser control. A pull-down resistor is built in.
Pulled down
O FSTA control. A pull-down resistor is built in.
Pulled down
O EFBAL control. A pull-down resistor is built in.
Pulled down
O SP8 control. A pull-down resistor is built in.
Pulled down
— Digital system power supply
Synchronizing signal detection output. Outputs a high level if the synchronizing signal detected
O from the EFM signal and the internally generated synchronizing signal match.
Undefined
EFM data playback clock monitor. 4.3218 MHz when the phase is locked.
O (Note that this output is only provided in test mode. This pin outputs a low level during normal
mode operation.)
Low output
O Sled off control output
High output
O
Sled feed output
O
Low output
Low output
I Limit switch detection input
O Digital output (EIAJ format)
Undefined
O Segment output (6)
Low output
O Segment output (5)
Low output
O Segment output (4)
Low output
O Segment output (3)
Low output
O Segment output (2)
Low output
O Segment output (1)
Low output
O Common driver output (3)
Low output
O Common driver output (2)
Low output
O Common driver output (1)
Low output
— Digital system ground. This pin must be connected to 0 V.
— LCD drive bias 1/2 VDD monitor
I Key matrix input (4). A pull-up resistor is built in.
I Key matrix input (3). A pull-up resistor is built in.
I Key matrix input (2). A pull-up resistor is built in.
I Key matrix input (1). A pull-up resistor is built in.
O Key matrix common output (1). This is an open-drain output.
Hi-Z
O Key matrix common output (2). This is an open-drain output.
Hi-Z
O Random mode indicator output (Low: random mode, high: modes other than random mode.)
Hi-Z
Remote controller identifier input (3). This pin functions as an output pin set to the low level
during resets (when the *RES pin is low) and for a few milliseconds after the *RES pin
I/O switches to the high level. Therefore, applications that will set this pin high must connect an
external pull-up resistor to this pin.
Low output
Continued on next page.
No. 6020-6/11

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