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30044-23 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer 30044-23
Beschreibung Geode GXm Processor Integrated x86 Solution with MMX Support
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 30 Seiten
30044-23 Datasheet, Funktion
April 2000
Geode™ GXm Processor
Integrated x86 Solution with MMX Support
General Description
The National Semiconductor® Geode™ GXm processor
is an advanced 32-bit x86 compatible processor offering
high performance, fully accelerated 2D graphics, a 64-bit
synchronous DRAM controller and a PCI bus controller,
all on a single chip that is compatible with Intel’s MMX
technology.
The GXm processor core is a proven design that offers
competitive CPU performance. It has integer and floating
point execution units that are based on sixth-generation
technology. The integer core contains a single, six-stage
execution pipeline and offers advanced features such as
operand forwarding, branch target buffers, and extensive
write buffering. A 16 KB write-back L1 cache is accessed
in a unique fashion that eliminates pipeline stalls to fetch
operands that hit in the cache.
In addition to the advanced CPU features, the GXm pro-
cessor integrates a host of functions which are typically
implemented with external components. A full-function
graphics accelerator provides pixel processing and ren-
dering functions.
A separate on-chip video buffer enables >30 fps MPEG1
video playback when used together with the CS5530 I/O
companion chip. Graphics and system memory accesses
are supported by a tightly-coupled synchronous DRAM
(SDRAM) memory controller. This tightly coupled memory
subsystem eliminates the need for an external L2 cache.
The GXm processor includes Virtual System Architec-
ture® (VSA™ technology) enabling XpressGRAPHICS
and XpressAUDIO subsystems as well as generic emula-
tion capabilities. Software handler routines for the Xpress-
GRAPHICS and XpressAUDIO subsystems can be
included in the BIOS and provide compatible VGA and 16-
bit industry standard audio emulation. XpressAUDIO tech-
nology eliminates much of the hardware traditionally asso-
ciated with audio functions.
Geode™ GXm Processor Internal Block Diagram
Write-Back
Cache Unit
C-Bus
MMU
Integer
Unit
Internal Bus Interface Unit
X-Bus
FPU
Integrated
Functions
Graphics
Pipeline
Memory
Controller
Display
Controller
PCI
Controller
SDRAM Port
CS5530
(CRT/LCD TFT)
PCI Bus
National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation.
Geode and VSA are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
© 2000 National Semiconductor Corporation
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30044-23 Datasheet, Funktion
Table of Contents (Continued)
6.0 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.1 APM SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.2 CPU SUSPEND COMMAND REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.3 SUSPEND MODULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.4 3-VOLT SUSPEND MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.5 SUSPEND MODE AND BUS CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
6.5.1
6.5.2
6.5.3
6.5.4
Initiating Suspend with SUSP# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Initiating Suspend with HALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Responding to a PCI Access During Suspend Mode . . . . . . . . . . . . . . . . . . . . . . 177
Stopping the Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.6 GXM PROCESSOR SERIAL BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.6.1 Serial Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.7 POWER MANAGEMENT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
7.0 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
7.1 PART NUMBERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
7.2 ELECTRICAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
Power/Ground Connections and Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Power Sequencing the Core and I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
NC-Designated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Pull-Up and Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Unused Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
7.3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
7.4 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7.5 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
7.6 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
8.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
8.1 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
8.1.1 Heatsink Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
8.2 MECHANICAL PACKAGE OUTLINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
9.0 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
9.1 GENERAL INSTRUCTION SET FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
Prefix (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
mod and r/m Byte (Memory Addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
reg Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
s-i-b Byte (Scale, Indexing, Base) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
9.2 CPUID INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
9.2.1 Standard CPUID Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
9.2.2 Extended CPUID Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
9.3 PROCESSOR CORE INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
9.4 FPU INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
9.5 MMX INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
9.6 NATIONAL SEMICONDUCTOR EXTENDED MMX INSTRUCTION SET . . . . . . . . . . . . . 234
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30044-23 pdf, datenblatt
Architecture Overview (Continued)
The CS9210 converts the digital RGB output of the
CS5530 I/O companion chip to the digital output suitable
for driving a dual-scan color STN (DSTN) flat panel LCD.
It connects to the digital RGB output of a GXm processor
or 55x0 and drives the graphics data onto a dual-scan flat
panel LCD. It can drive all standard dual-scan color STN
flat panels up to 1024x768 resolution. Figure 1-3 shows
an example of a CS9210 interface in a typical GXm Inte-
grated Subsystem.
Pixel Data 18
Geode™ GXm
Processor
Geode™
CS5530
I/O
Companion
Pixel Port
(Control & Data) 24
Serial
Configuration
4
Geode™
CS9210
DSTN
Controller
Address Control 13
DRAM Data 16
Address Control 13
DRAM Data 16
DRAM-A
256Kx16 Bit
DRAM-B
256Kx16 Bit
Panel Control
Panel Data
6
24
DSTN
LCD
Figure 1-3. CS9210 Interface System Diagram
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