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Número de pieza | A6173081 | |
Descripción | 128K X 8 BIT HIGH SPEED CMOS SRAM | |
Fabricantes | AMIC Technology | |
Logotipo | ||
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No Preview Available ! A616316 Series
Preliminary
64K X 16 BIT HIGH SPEED CMOS SRAM
Document Title
64K X 16 BIT HIGH SPEED CMOS SRAM
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
July 14, 2000
Remark
Preliminary
PRELIMINARY (July, 2000, Version 0.0)
AMIC Technology, Inc.
1 page A616316 Series
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
IN, IN/OUT Volt to GND . . . . . . . . -0.5V to VCC + 0.5V
Operating Temperature, Topr . . . . . . . . . . 0°C to +70°C
Storage Temperature, Tstg . . . . . . . . . -55°C to +125°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . 1.0W
Soldering Temp. & Time . . . . . . . . . . . . 260°C, 10 sec
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = 0°C to + 70°C, VCC = 5V±10%, GND = 0V)
Symbol
Parameter
ILI
Input Leakage
A616316-12
Min. Max.
-2
A616316-15
Min. Max.
-2
Unit
µA
Conditions
VIN = GND to VCC
ILO Output Leakage
- 2 - 2 µA CE = VIH, OE = VIH
VI/O = GND to VCC
ICC1 (2) Dynamic Operating
Current
- 170 - 165 mA CE = VIL, II/O = 0 mA
Min. Cycle, Duty = 100%
ISB
Standby Power
ISB1 Supply Current
- 25 - 25 mA CE = VIH
- 8 - 8 mA CE ≥ VCC - 0.2V,
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
VOL Output Low Voltage
- 0.4 - 0.4 V IOL = 8 mA
VOH Output High Voltage
2.4
-
2.4
-
V IOH = -4 mA
Notes: 1. VIL = -3.0V for pulses less than 20 ns.
2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns.
PRELIMINARY (July, 2000, Version 0.0)
4
AMIC Technology, Inc.
5 Page A616316 Series
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
Address
CE
HB, LB
tAS1
WE
DATA IN
DATA OUT
tWHZ4
tWC
tAW
tCW
tBW2
tWP
tDW
tWR3
tDH
tOW
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and, or LB ).
3. tWR is measured from the earliest of CE or WE or ( HB and, or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (July, 2000, Version 0.0)
10
AMIC Technology, Inc.
11 Page |
Páginas | Total 15 Páginas | |
PDF Descargar | [ Datasheet A6173081.PDF ] |
Número de pieza | Descripción | Fabricantes |
A617308 | 128K X 8 BIT HIGH SPEED CMOS SRAM | AMIC Technology |
A6173081 | 128K X 8 BIT HIGH SPEED CMOS SRAM | AMIC Technology |
A6173081S-12 | 128K X 8 BIT HIGH SPEED CMOS SRAM | AMIC Technology |
A6173081S-15 | 128K X 8 BIT HIGH SPEED CMOS SRAM | AMIC Technology |
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