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PDF 33937A Data sheet ( Hoja de datos )
| Número de pieza | 33937A | |
| Descripción | Three phase field effect transistor pre-driver | |
| Fabricantes | NXP Semiconductors | |
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NXP Semiconductors
Technical Data
Three phase field effect transistor
pre-driver
Document Number: MC33937
Rev. 9.0, 7/2016
33937A
The 33937A is a field effect transistor (FET) pre-drivers designed for three
phase motor control and similar applications. The integrated circuit (IC) uses
SMARTMOS technology.
The IC contains three high-side FET pre-drivers and three low-side FET pre-
drivers. Three external bootstrap capacitors provide gate charge to the high-
side FETs.
The IC interfaces to a MCU via six direct input control signals, an SPI port for
device setup and asynchronous reset, enable and interrupt signals. Both 5.0
and 3.0 V logic level inputs are accepted and 5.0 V logic level outputs are
provided.
THREE PHASE PRE-DRIVER
Features
• Extended operating range from 6.0 V to 58 V covers 12 V and 42 V systems
• Gate drive capability of 1.0 A to 2.5 A
• Fully specified from 8.0 V to 40 V covers 12 and 24 V automotive systems
• Protection against reverse charge injection from CGD and CGS of external
FETs
• Includes a charge pump to support full FET drive at low battery voltages
• Dead time is programmable via the SPI port
• Simultaneous output capability enabled via safe SPI command
EK SUFFIX (Pb-FREE)
98ASA99334D
54-PIN SOICW-EP
Applications
Automotive systems
• Cooling fan
• Water pump
• Actuator controls
• Fuel pump
• Electro-hydraulic and electric power steering
• Engine control
• Motor control
VSYS
MCU
OR
DSP
33937
VPUMP
PUMP
VPWR
VLS
VSUP
PA_HS_G
PB_HS_G
PC_HS_G
VDD
PA_HS_S
VSS
PB_HS_S
PC_HS_S
3
3
3
PX_HS
PX_LS
PHASEX
PA_LS_G
CS PB_LS_G
SI PC_LS_G
SCLK
SO PX_LS_S
RST
INT
EN1
EN2
AMP_P
AMP_N
GND AMP_OUT
RSEN
Figure 1. 33937A simplified application diagram
© 2016 NXP B.V.
1 page  
Table 2. 33937A pin definitions (continued)
Pin
Pin name Pin function
Formal name
Definition
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30, 31
32
34
35
36
37
38
39
40
41
42
43
44
PHASEB
PHASEC
PA_HS
PA_LS
VDD
PB_HS
PB_LS
INT
CS
SI
SCLK
SO
PC_LS
PC_HS
AMP_OUT
AMP_N
AMP_P
OC_OUT
OC_TH
VSS
GND
VLS_CAP
PC_LS_S
PC_LS_G
PC_HS_S
PC_HS_G
PC_BOOT
PB_LS_S
PB_LS_G
PB_HS_S
PB_HS_G
PB_BOOT
PA_LS_S
Digital Output
Phase B
Digital Output
Phase C
Digital Input Phase A High-side
Totem Pole output of Phase B comparator. This output is low when the voltage on
PB_HS_S (Source of high-side FET) is less than 50% of VSUP
Totem Pole output of Phase C comparator. This output is low when the voltage on
PC_HS_S (Source of high-side FET) is less than 50% of VSUP
Active low input logic signal enables the high-side driver for Phase A
Digital Input Phase A Low-side Active high input logic signal enables the low-side driver for Phase A
Analog
Output
VDD Regulator
VDD regulator output capacitor connection.
Digital Input Phase B High-side Active low input logic signal enables the high-side driver for Phase B
Digital Input Phase B Low-side Active high input logic signal enables the low-side driver for Phase B
Digital Output
Interrupt
Interrupt pin output
Digital Input
Chip Select
Chip Select input. It frames SPI commands and enables SPI port
Digital Input
Serial In
Input data for SPI port. Clocked on the falling edge of SCLK, MSB first
Digital Input
Serial Clock
Clock for SPI port and typically is 3.0 MHz
Digital Output
Serial Out
Output data for SPI port. Tri-state until CS becomes low
Digital Input Phase C Low-side Active high input logic signal enables the low-side driver for Phase C
Digital Input Phase C High-side Active low input logic signal enables the high-side driver for Phase C
Analog
Output
Amplifier Output
Output of the current-sensing amplifier
Analog Input
Amplifier Invert
Inverting input of the current-sensing amplifier
Analog Input Amplifier Non-Invert Non-inverting input of the current-sensing amplifier
Digital Output Overcurrent Out
Totem pole digital output of the overcurrent comparator
Analog Input Overcurrent Threshold Threshold of the overcurrent detector
Ground Voltage Source Supply Ground reference for logic interface and power supplies
Ground
Ground
Substrate and ESD reference, connect to VSS
Analog
Output
VLS Regulator Output VLS Regulator connection for additional output capacitor, providing low-
Capacitor
impedance supply source for low-side gate drive
Power Input
Phase C Low-side
Source
Source connection for Phase C low-side FET
Power Output
Phase C Low-side
Gate Drive
Gate drive output for Phase C low-side
Power Input
Phase C High-side
Source
Source connection for Phase C high-side FET
Power Output
Phase C High-side
Gate Drive
Gate Drive for output Phase C high-side FET
Analog Input Phase C Bootstrap Bootstrap capacitor for Phase C
Power Input
Phase B Low-side
Source
Source connection for Phase B low-side FET
Power Output
Phase B Low-side
Gate Drive
Gate Drive for output Phase B low-side
Power Input
Phase B High-side
Source
Source connection for Phase B high-side FET
Power Output
Phase B High-side
Gate Drive
Gate Drive for output Phase B high-side
Analog Input Phase B Bootstrap Bootstrap capacitor for Phase B
Power Input
Phase A Low-side
Source
Source connection for Phase A low-side FET
NXP Semiconductors
33937A
5
5 Page 
Table 4. Static electrical characteristics (continued)
Characteristics noted under conditions 8.0 V ≤ VPWR = VSUP ≤ 40 V, -40 °C ≤ TA ≤ 135 °C, unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit Notes
Overcurrent comparator
VCM
VOS_OC
VOC_HYST
VOH
VOL
Common Mode Input Range
Input Offset Voltage
Overcurrent Comparator Threshold Hysteresis
Output Voltage
• High Level at IOH = -500 µA
• Low Level at IOL = 500 µA
2.0 – VDD-0.02 V
-50 – 50 mV
50 300 mV
0.85 VDD
–
VDD
V
– – 0.5
(23)
(22)
Hold off circuit
IHOLD
Hold Off Current (At Each GATE Pin)
• 3.0 V < VSUP < 40 V, VGATE = 1.0 V
10 – 300 µA (24)
Phase comparator
VIH_TH
High Level Input Voltage Threshold
VIL_TH
Low Level Input Voltage Threshold
VOH High Level Output Voltage at IOH = -500 µA
VOL Low Level Output Voltage at IOL = 500 µA
RIN High-side Source Input Resistance
Desaturation detector
VDES_TH
Desaturation Detector Threshold
0.5 VSUP
0.3 VSUP
0.85 VDD
–
–
– 0.65 VSUP V
– 0.45 VSUP V
– VDD V
– 0.5 V
40 – kΩ (22), (27)
1.2 1.4 1.6
V (25)
Current sense amplifier
RS Recommended External Series Resistor (See Figure 9)
RFB
Recommended External Feedback Resistor (See Figure 9)
• Limited by the Output Voltage Dynamic Range
– 1.0 – kW
5.0 – 15 kW (28)
VID
VCM
VOS
δVOS/δT
Ib
Maximum Input Differential Voltage (See Figure 9)
• VID = VAMP_P - VAMP_N
Input Common Mode Range
Input Offset Voltage
• RS = 1.0 kΩ, VCM = 0.0 V
Input Offset Voltage Drift
Input Bias Current
• VCM = 2.0 V
-800
–
+800
mV
-0.5 – 3.0 V (22), (26)
-15 – +15 mV
–
-10
–
µV/°C
(22)
-200
–
+200
nA
Notes
22. This parameter is a design characteristic, not production tested.
23. As long as one input is in the common mode range there is no phase inversion on the output.
24. The hold off circuit is designed to operate over the full operating range of VSUP. The specification indicates the conditions used in production test.
Hold off is activated at VPOR or VTHVLS.
25. Desaturation is measured as the voltage drop below VSUP, thus the threshold is compared to the drain-source voltage of the external High-side
FET. See Figure 5.
26. As long as one input is within VCM the output is guaranteed to have the correct phase. Exceeding the common mode rails on one input will not
cause a phase inversion on the output.
27. Input resistance is impedance from the high-side source and is referenced to VSS. Approximate tolerance is ±20%.
28. The current sense amplifier is unity gain stable with a phase margin of approximately 45°. See Figure 10.
NXP Semiconductors
33937A
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 33937A.PDF ] | |
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