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PDF ADT7476A Data sheet ( Hoja de datos )
| Número de pieza | ADT7476A | |
| Descripción | Remote Thermal Controller and Voltage Monitor | |
| Fabricantes | ON Semiconductor | |
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ADT7476A
Remote Thermal Controller
and Voltage Monitor
The ADT7476A controller is a thermal monitor and multiple PWM
fan controller for noise-sensitive or power-sensitive applications
requiring active system cooling. The ADT7476A can drive a fan using
either a low or high frequency drive signal and can monitor the
temperature of up to two remote sensor diodes plus its own internal
temperature. The part also measures and controls the speed of up to
four fans, so the fans operate at the lowest possible speed for minimum
acoustic noise.
The automatic fan speed control loop optimizes fan speed
for a given temperature. The effectiveness of the system’s thermal
solution can be monitored using the THERM input. The ADT7476A
also provides critical thermal protection to the system using the
bidirectional THERM pin as an output to prevent system or
component overheating.
Features
• Monitors Up to Five Voltages
• Improved TACH and PWM Performance
• Controls and Monitors Up to Four Fans
• High and Low Frequency Fan Drive Signal
• One On-Chip and Two Remote Temperature Sensors
• Extended Temperature Measurement Range Up to 191°C
• Automatic Fan Speed Control Mode Controls System Cooling Based
on Measured Temperature
• Enhanced Acoustic Mode Dramatically Reduces User Perception of
Changing Fan Speeds
• Thermal Protection Feature via THERM Output
• Monitors Performance Impact of Intel® Pentium® 4 Processor
• Thermal Control Circuit via THERM Input
• 3-wire and 4-wire Fan Speed Measurement
• Limit Comparison of All Monitored Values
• 5.0 V Support on all TACH and PWM Channels
• Meets SMBus 2.0 Electrical Specifications
• This Device is Pb-Free, Halogen Free and is RoHS Compliant
www.onsemi.com
QSOP−24 NB
CASE 492B
PIN ASSIGNMENT
SDA 1
24 PWM1/XTO
SCL 2
GND 3
VCC 4
VID0/GPIO0 5
VID1/GPIO1 6
VID2/GPIO2 7
VID3/GPIO3 8
ADT7476A
(Top View)
23 VCCP
22 +2.5VIN/THERM
21 +12VIN/VID5
20 +5VIN
19 VID4/GPIO4
18 D1+
17 D1−
TACH3
PWM2/
SMBALERT
TACH1
9
10
11
16 D2+
15 D2−
14 *
TACH2 12
13 PWM3/ADDREN
*TACH4/THERM/SMBALERT/GPIO6/ADDR SELECT
MARKING DIAGRAMS
ADT7476AARQZ
#YYWW
xxxx
ADT7476AARQZ = Specific Device Code
# = Pb-Free Package
YYWW
= Date Code
xxxx
= Assembly Lot Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 68 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 7
1
Publication Order Number:
ADT7476A/D
1 page  
ADT7476A
Table 4. PIN ASSIGNMENT
Pin No.
1
2
3
4
Mnemonic
SDA
SCL
GND
VCC
Description
Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pullup.
Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pullup.
Ground Pin.
Power Supply. Powered by 3.3 V standby, if monitoring in low power states is required. VCC is also
monitored through this pin.
5
VID0/
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
GPIO0
General-Purpose Open Drain Digital I/O.
6
VID1/
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
GPIO1
General-Purpose Open Drain Digital I/O.
7
VID2/
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
GPIO2
General-Purpose Open Drain Digital I/O.
8
VID3/
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
GPIO3
General-Purpose Open Drain Digital I/O.
9
TACH3
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.
10
PWM2/
Digital Output (Open Drain). Requires 10 kW typical pullup. Pulse width modulated output to control Fan
2 speed. Can be configured as a high or low frequency drive.
SMBALERT
Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal
out-of-limit conditions.
11
TACH1
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1.
12
TACH2
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2.
13
PWM3
Digital I/O (Open Drain). Pulse width modulated output to control the speed of Fan 3 and Fan 4.
Requires 10 kW typical pullup. Can be configured as a high or low frequency drive.
ADDREN
If pulled low on powerup, the ADT7476A enters address select mode, and the state of Pin 14 (ADDR
SELECT) determines the ADT7476A’s slave address.
14
TACH4/
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.
THERM/
SMBALERT/
GPIO6/
ADDR SELECT
Alternatively, the pin can be reconfigured as a bidirectional THERM pin. Times and monitors assertions
on the THERM input. For example, it can be connected to the PROCHOT output of Intel’s Pentium® 4
processor or to the output of a trip point temperature sensor. Can be used as an output to signal
overtemperature conditions.
Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal
out-of-limit conditions.
General-Purpose Open Drain Digital I/O.
If in address select mode, the logic state of this pin defines the SMBus device address.
15 D2– Cathode Connection to Second Thermal Diode.
16 D2+ Anode Connection to Second Thermal Diode.
17 D1– Cathode Connection to First Thermal Diode.
18 D1+ Anode Connection to First Thermal Diode.
19
VID4/
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
GPIO4
General-Purpose Open Drain Digital I/O.
20
+5.0 VIN
Analog Input. Monitors 5.0 V power supply.
21
+12 VIN/
Analog Input. Monitors 12 V power supply.
VID5
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
22
+2.5 VIN/
Analog Input. Monitors 2.5 V supply, typically a chipset voltage.
THERM
Alternatively, this pin can be reconfigured as a bidirectional/omnidirectional THERM pin. Can be used to
time and monitor assertions on the THERM input. For example, can be connected to the PROCHOT
output of Intel’s Pentium® 4 processor or to the output of a trip point temperature sensor. Can be used as
an output to signal overtemperature conditions.
23
VCCP
Analog Input. Monitors processor core voltage (0 V to 3 V).
24
PWM1/
Digital Output (Open Drain). Pulse width modulated output to control the speed of Fan 1. Requires 10 kW
typical pullup.
XTO
Also functions as the output from the XOR tree in XOR test mode.
www.onsemi.com
5
5 Page 
ADT7476A
1
SCL
91
9
SDA
0
START BY
MASTER
1 0 1 1 A1 A0
FRAME 1
SERIAL BUS ADDRESS BYTE
R/W D7
ACK. BY
ADT7476A
D6 D5 D4 D3 D2 D1 D0
NO ACK. BY
FRAME 2
MASTER
DATA BYTE FROM ADT7476A
STOP BY
MASTER
Figure 20. Reading Data from a Previously Selected Register
Write Operations
The SMBus specification defines several protocols for
different types of read and write operations. The ones used
in the ADT7476A are discussed below. The following
abbreviations are used in the diagrams:
• S – START
• P – STOP
• R – READ
• W– WRITE
• A – ACKNOWLEDGE
• A – NO ACKNOWLEDGE
The ADT7476A uses the following SMBus write protocols.
Send Byte
In this operation, the master device sends a single
command byte to a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA, and
the transaction ends.
For the ADT7476A, the send byte protocol is used to write
a register address to RAM for a subsequent single-byte read
from the same address. This operation is illustrated in
Figure 21.
12
3 4 56
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
AP
Figure 21. Setting a Register Address for
Subsequent Read
If the master is required to read data from the register
immediately after setting up the address, it can assert a repeat
start condition immediately after the final ACK and carry
out a single byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte
and one data byte to the slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA,
and the transaction ends.
This operation is illustrated in Figure 22.
12
3 4 5 6 78
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
A DATA
AP
Figure 22. Single-byte Write to a Register
Read Operations
The ADT7476A uses the following SMBus read
protocols.
Receive Byte
This operation is useful when repeatedly reading a single
register. The register address is set up beforehand. In this
operation, the master device receives a single byte from a
slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by the read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA, and
the transaction ends.
In the ADT7476A, the receive byte protocol is used to
read a single byte of data from a register whose address has
previously been set by a send byte or write byte operation.
This operation is illustrated in Figure 23.
12
34
S
SLAVE
ADDRESS
R
A
DATA
56
AP
Figure 23. Single-byte Read from a Register
www.onsemi.com
11
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| PDF Descargar | [ Datasheet ADT7476A.PDF ] | |
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