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PDF PE42421 Data sheet ( Hoja de datos )
| Número de pieza | PE42421 | |
| Descripción | RF Switch | |
| Fabricantes | Peregrine Semiconductor | |
| Logotipo |  |
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Product Description
The PE42421 UltraCMOS® RF switch is designed to
cover a broad range of applications from 10 MHz
through 3000 MHz. This reflective switch integrates
on-board CMOS control logic with a low voltage
CMOS-compatible control interface, and can be
controlled using either single-pin or complementary
control inputs. Using a nominal +3-volt power supply
voltage, a typical input 1 dB compression point of
+33.5 dBm can be achieved.
The PE42421 SPDT RF switch is manufactured on
Peregrine’s UltraCMOS® process, a patented
variation of silicon-on-insulator (SOI) technology on
a sapphire substrate, offering the performance of
GaAs with the economy and integration of
conventional CMOS.
Figure 1. Functional Diagram
RFC
RF1
ESD
RF2
ESD
CMOS
Control
Driver
CTRL CTRL or VDD
71-0015-01
Product Specification
PE42421
SPDT UltraCMOS®
10 MHz – 3.0 GHz RF Switch
Features
Single-pin or complementary CMOS
logic control inputs
Low insertion loss: 0.35 dB at
1000 MHz, 0.5 dB at 2000 MHz
Isolation of 30 dB at 1000 MHz, 20 dB
at 2000 MHz
Typical input 1 dB compression point
of +33.5 dBm
1.8V minimum power supply voltage
SC-70 package
Figure 2. Package
6-lead SC-70
Document No. 70-0396-03 │ www.psemi.com
©2010-2013 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Page 1 of 9
1 page  
PE42421
Product Specification
Evaluation Kit
The SPDT switch EK Board was designed to ease
customer evaluation of Peregrine’s PE42421. The
RF common port is connected through a 50Ω
transmission line via the top SMA connector, J1.
RF1 and RF2 are connected through 50Ω
transmission lines via SMA connectors J2 and J3,
respectively. A through 50Ω transmission is
available via SMA connectors J4 and J5. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.0476”, trace
gaps of 0.030”, dielectric thickness of 0.028”,
metal thickness of 0.0021” and εr of 4.4.
J6 and J7 provide a means for controlling DC and
digital inputs to the device. J6-1 is connected to
the device VDD or CTRL input. J7-1 is connected
to the device CTRL input.
Figure 5. Evaluation Board Layouts
Peregrine Specification 101-0162-02
Figure 6. Evaluation Board Schematic
Peregrine Specification 102-0756-01
J4 1
N/A
T-line Description
--
Model = CPWG
H = 28 mils
T = 2.1 mils
W = 47 mils
G = 30 mils
Er = 4.4
J7
CNTL
R2
1 K Ohm
1 J5
N/A
General Comments
Transmission lines connected to J1, J2, and J3 should have exactly the
same electrical length
The path from J2 to J3 including the distance through the part should
have the same length as J4 and J5 and be in parallel to J4 to J5
J1 1
RFC
C1
0.5pF
SEEASSYNOTE 2
C2
0.5pF
SEEASSYNOTE 2
Document No. 70-0396-03 │ www.psemi.com
U1
PE42421/SC70-6
4 CTRL RF_2 3
5 RFC GND 2
6 VDD RF_1 1
1 J3
RF2
1 J2
RF1
R1
1 K Ohm
J6
CNTLX/VDD
Notes: Add two 0.5 pF caps in series to be shunted on the J1 SMA input
Solder C1 side 1 to the RF trace close to the J1 pin
Solder C1 side 2 to C2 side 1
Solder C2 side 2 to ground
©2010-2013 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Page 5 of 9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet PE42421.PDF ] | |
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