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R5F117AC Schematic ( PDF Datasheet ) - Renesas

Teilenummer R5F117AC
Beschreibung MCU
Hersteller Renesas
Logo Renesas Logo 




Gesamt 30 Seiten
R5F117AC Datasheet, Funktion
RL78/I1D
RENESAS MCU
1. OUTLINE
1.1 Features
Ultra-low power consumption technology
• VDD = 1.6 V to 3.6 V
• HALT mode
• STOP mode
• SNOOZE mode
RL78 CPU core
• CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be changed
from high speed (0.04167 s: @ 24 MHz operation with
high-speed on-chip oscillator) to ultra-low speed (66.6
s: @ 15 kHz operation with low-speed on-chip
oscillator clock)
• Multiply/divide/multiply & accumulate instructions are
supported.
• Address space: 1 MB
• General-purpose registers: (8-bit register 8) 4 banks
• On-chip RAM: 0.7 to 3 KB
Code flash memory
• Code flash memory: 8 to 32 KB
• Block size: 1 KB
• Prohibition of block erase and rewriting (security
function)
• On-chip debug function
• Self-programming (with boot swap function/flash shield
window function)
Data flash memory
• Data flash memory: 2 KB
• Back ground operation (BGO): Instructions can be
executed from the program memory while rewriting the
data flash memory.
• Number of rewrites: 1,000,000 times (TYP.)
• Voltage of rewrites: VDD = 1.8 to 3.6 V
High-speed on-chip oscillator
• Select from 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4
MHz, 3 MHz, 2 MHz, and 1 MHz
• High accuracy: ±1.0% (VDD = 1.8 to 3.6 V, TA = -20 to
+85°C)
Middle-speed on-chip oscillator
• Selectable from 4 MHz, 2 MHz, and 1 MHz.
Operating ambient temperature
• TA = -40 to +105°C (G: Industrial applications)
Power management and reset function
• On-chip power-on-reset (POR) circuit
• On-chip voltage detector (LVD) (Select interrupt and
reset from 12 levels)
R01DS0244EJ0200 Rev. 2.00
Jan 16, 2015
Datasheet
R01DS0244EJ0200
Rev. 2.00
Jan 16, 2015
Data transfer controller (DTC)
• Transfer modes: Normal transfer mode, repeat transfer
mode, block transfer mode
• Activation sources: Activated by interrupt sources.
• Chain transfer function
Event link controller (ELC)
• Event signals of 20 types can be linked to the specified
peripheral function.
Serial interfaces
• CSI: 2 channels
• UART: 1 channel
• I2C/simplified I2C: 2 channels
Timers
• 16-bit timer: 4 channels
• 12-bit interval timer: 1 channel
• 8-bit interval timer: 4 channels
• Real-time clock: 1 channel (calendar for 99 years, alarm
function, and clock correction function)
• Watchdog timer: 1 channel
A/D converter
• 8/12-bit resolution A/D converter (VDD = 1.6 to 3.6 V)
• Analog input: 6 to 17 channels
• Internal reference voltage (1.45 V) and temperature
sensor
Comparator
• 2 channels
• Operating modes: Comparator high-speed mode,
comparator low-speed mode, window mode
Operational amplifier
• 4 channels
I/O ports
• I/O port: 14 to 42 (N-ch open drain I/O [withstand
voltage of 6 V]: 4, N-ch open drain I/O [VDD withstand
voltage]: 3 to 7)
• Can be set to N-ch open drain, TTL input buffer, and on-
chip pull-up resistor
• Different potential interface: Can connect to a 1.8/2.5 V
device
• On-chip key interrupt function
• On-chip clock output/buzzer output controller
Others
• On-chip BCD (binary-coded decimal) correction circuit
• On-chip data operation circuit
Remark The functions mounted depend on the
product. See 1.6 Outline of Functions.
Page 1 of 99






R5F117AC Datasheet, Funktion
RL78/I1D
1.3.2 24-pin products
• 24-pin plastic HWQFN (4 4 mm, 0.5 mm pitch)
1. OUTLINE
AVSS
P14/ANI4/IVCMP0/AMP0O
P13/ANI3/AMP0-
P12/ANI2/AMP0+
P40/TOOL0
RESET
INDEX MARK
Exposed die pad
18 17 16 15 14 13
19 12
20 11
21 10
22 9
23 8
241 2 3 4 5 6 7
P51/KR0/SCK01/SCL01/TI02/TO02
P52/KR1/SI01/SDA01/TI03/TO03
P53/KR2/SO01/VCOUT0
P54/SO00/TxD0/INTP1/TOOLTXD
P55/SI00/RxD0/SDA00/INTP2/TOOLRXD
P56/SCK00/SCL00/INTP3
Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Caution 2. Make AVSS pin the same potential as VSS pin.
Caution 3. Make AVDD pin the same potential as VDD pin.
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. It is recommended to connect an exposed die pad to VSS.
Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0
(PIOR0).
R01DS0244EJ0200 Rev. 2.00
Jan 16, 2015
Page 6 of 99

6 Page









R5F117AC pdf, datenblatt
RL78/I1D
1.5 Block Diagram
1.5.1 48-pin products
TI00
TO00
TI01
TO01
TI02
TO02
TI03
TO03
TIMER ARRAY UNIT 0
(4ch)
ch00
ch01
ch02
ch03
8-BIT INTERVAL TIMER 0
ch00
ch01
8-BIT INTERVAL TIMER 1
ch10
ch11
RxD0
TxD0
SCK00
SI00
SO00
SSI00
SCK01
SI01
SO01
SCL00
SDA00
SCL01
SDA01
SERIAL ARRAY UNIT0
(2ch)
UART0
CSI00
CSI01
IIC00
IIC01
EVENT LINK CONTROLLER
(ELC)
CODE FLASH:
32 KB
DATA FLASH:
2 KB
BCD CORRECTION
CIRCUIT
DATA OPERATION
CIRCUIT (DOC)
RL78 CPU CORE
MULDIV
INT
DATA TRANSFER
CONTROLLER (DTC)
RAM 3 KB
CLOCK GENERATOR
+
RESET CIRCUIT
RESET
MAIN SYSTEM CLOCK
GENERATOR
1 to 20 MHz
X1 X2/EXCLK
SUBSYSTEM CLOCK
GENERATOR
32.768 kHz
POR/
LVD
HIGH-SPEED
ON-CHIP
OSCILLATOR
24 MHz
MIDDLE-SPEED
ON-CHIP
OSCILLATOR
4 MHz
LOW-SPEED
ON-CHIP
OSCILLATOR
15 kHz
XT1 XT2/EXCLK
REGULATOR
REGC
VDD
VSS TOOLRXD/P55,
TOOLTXD/P54
WATCHDOG TIMER
(WDT)
CRC
FREQUENCY
MEASUREMENT CIRCUIT
1. OUTLINE
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 12
Port 13
5 P00 to P04
8 P10 to P17
6 P20 to P25
4 P30 to P33
P40
8 P50 to P57
4 P60 to P63
4 P121 to P124
P130
P137
ON-CHIP DEBUG
TOOL0/P40
CLOCK OUTPUT/
BUZZER OUTPUT
CONTROLLER
KEY INTERRUPT
4ch
PCLBUZ0
PCLBUZ1
4 KR0 to KR3
EXTERNAL INTERRUPT
7ch
7
INTP0 to INTP6
REAL TIME CLOCK
RTC1HZ
12-BIT INTERVAL
TIMER
A/D CONVERTER
(16ch)
15
ANI2 to ANI13,
ANI16 to ANI18
ANI0/AVREFP
ANI1/AVREFM
COMPARATOR (2ch)
COMPARATOR 0
COMPARATOR 1
VCOUT0
IVCMP0
IVREF0
VCOUT1
IVCMP1
IVREF1
OPERATIONAL
AMPLIFIER (4ch)
OPERATIONAL
AMPLIFIER 0
OPERATIONAL
AMPLIFIER 1
OPERATIONAL
AMPLIFIER 2
OPERATIONAL
AMPLIFIER 3
AMP0+
AMP0-
AMP0O
AMP1+
AMP1-
AMP1O
AMP2+
AMP2-
AMP2O
AMP3+
AMP3-
AMP3O
R01DS0244EJ0200 Rev. 2.00
Jan 16, 2015
Page 12 of 99

12 Page





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