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R5F11EAAASP Schematic ( PDF Datasheet ) - Renesas

Teilenummer R5F11EAAASP
Beschreibung MCU
Hersteller Renesas
Logo Renesas Logo 




Gesamt 30 Seiten
R5F11EAAASP Datasheet, Funktion
RL78/G1G
RENESAS MCU
1. OUTLINE
1.1 Features
Ultra-low power consumption technology
• VDD = single power supply voltage of 2.7 to 5.5 V
• HALT mode
• STOP mode
• SNOOZE mode
RL78 CPU core
• CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be changed
from high-speed (0.04167 μs: @ 24 MHz operation with
high-speed on-chip oscillator) to low-speed (1.0 μs: @1
MHz operation with high-speed on-chip oscillator)
• Multiply/divide/multiply & accumulate instructions are
supported.
• Address space: 1 MB
• General-purpose registers: (8-bit register × 8) × 4 banks
• On-chip RAM: 1.5 KB
Code flash memory
• Code flash memory: 8 to 16 KB
• Block size: 1 KB
• Prohibition of block erase and rewriting (security
function)
• On-chip debug function
• Self-programming (flash shield window function)
High-speed on-chip oscillator
• Select from 48 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz,
4 MHz, and 1 MHz
• High accuracy: ±2.0% (VDD = 2.7 to 5.5 V, TA = -20 to
+85°C)
Operating ambient temperature
• TA = -40 to +85°C
Power management and reset function
• On-chip power-on-reset (POR) circuit
• On-chip voltage detector (LVD) (Select interrupt and
reset from 6 levels)
Event link controller (ELC)
• Event signals of 18 to 19 types can be linked to the
specified peripheral function.
Serial interfaces
• CSI: 1 channel
• UART: 2 channels
• Simplified I2C: 1 channel
Datasheet
R01DS0241EJ0100
Rev. 1.00
Jul 31, 2014
Timer
• 16-bit timer: 7 channels
(Timer Array Unit (TAU): 4 channels, Timer RJ: 1
channel, Timer RD: 2 channels)
• 12-bit interval timer: 1 channel
• Watchdog timer: 1 channel (operable with the dedicated
low-speed on-chip oscillator)
A/D converter
• 8/10-bit resolution A/D converter (VDD = 2.7 to 5.5 V)
• Analog input: 8 to 12 channels
• Internal reference voltage (1.45 V) and temperature
sensor
Comparator
• 2 channels
Programmable gain amplifier
I/O port
• I/O port: 26 to 40
• Can be set to N-ch open drain, TTL input buffer, and on-
chip pull-up resistor
• Different potential interface: Can connect to a 2.5/3 V
device
• On-chip key interrupt function
• On-chip clock output/buzzer output controller
Others
• On-chip BCD (binary-coded decimal) correction circuit
Remark: The function mounted depend on the product.
See 1.6 Outline of Functions.
R01DS0241EJ0100 Rev. 1.00
Jul 31, 2014
Page 1 of 67






R5F11EAAASP Datasheet, Funktion
RL78/G1G
1.3.3 44-pin products
• 44-pin plastic LQFP (10 × 10 mm, 0.8 mm pitch)
1. OUTLINE
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/TO00/RxD1/PGAI/ANI16/TRJIO0
P00/TI00/TxD1/CMP0P/ANI17/(TRJO0)
P120/ANI19/CMP1P
33 3231 30 29 28 27 26 25 2423
34 22
35 21
36 20
37 19
38 18
39 17
40 16
41 15
42 14
43 13
44 1
2
3
4
5
6
7
8
12
9 1011
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/(TRJO0)
P30/INTP3/SCK00/SCL00/TRJO0
P70/KR0
P71/KR1
P72/KR2
P73/KR3
P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0)
P63
P62/SSI00
P61
P60
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 μF).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. The functions in parentheses shown in the above figure can be assigned by setting peripheral I/O redirection register 1
(PIOR1).
R01DS0241EJ0100 Rev. 1.00
Jul 31, 2014
Page 6 of 67

6 Page









R5F11EAAASP pdf, datenblatt
RL78/G1G
1. OUTLINE
Item
Clock output/buzzer output
8/10-bit resolution A/D converter
Comparator
PGA
Serial interface
Event link controller (ELC)
Vectored
interrupt
sources
Internal
External
Key interrupt
Reset
Power-on-reset circuit
Voltage detector
On-chip debug function
Power supply voltage
Operating ambient temperature
30-pin
32-pin
44-pin
R5F11EA8ASP,
R5F11EAAASP
R5F11EB8AFP,
R5F11EBAAFP
R5F11EF8AFP,
R5F11EFAAFP
2
• 2.44 kHz, 4.88 kHz, 9.77 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
8 channels
12 channels
2 channels
1 channel
• CSI: 1 channel/UART0: 1 channel/simplified I2C: 1 channel
• UART1: 1 channel
Event input: 18
Event trigger output: 6
Event input: 19
Event trigger output: 6
20
67
• Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
• Power-on-reset:
1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
2.75 V to 4.06 V (6 stages)
Provided
VDD = 2.7 to 5.5 V
TA = -40 to +85°C
4
(2/2)
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
R01DS0241EJ0100 Rev. 1.00
Jul 31, 2014
Page 12 of 67

12 Page





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