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PDF ADG633 Data sheet ( Hoja de datos )
| Número de pieza | ADG633 | |
| Descripción | Triple SPDT Switch / CMOS | |
| Fabricantes | Analog Devices | |
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CMOS, ±5 V/+5 V/+3 V, Triple SPDT Switch
ADG633
FEATURES
±2 V to ±6 V dual-supply operation
2 V to 12 V single-supply operation
Automotive temperature range: −40°C to +125°C
<0.2 nA leakage currents
52 Ω on resistance over full signal range
Rail-to-rail switching operation
16-lead LFCSP and TSSOP packages
Typical power consumption: <0.1 μW
TTL-/CMOS-compatible inputs
Package upgrades to 74HC4053 and MAX4053/MAX4583
APPLICATIONS
Automotive applications
Automatic test equipment
Data acquisition systems
Battery-powered systems
Communications systems
Audio and video signal routing
Relay replacement
Sample-and-hold systems
Industrial control systems
GENERAL DESCRIPTION
The ADG633 is a low voltage CMOS device comprising three
independently selectable single-pole, double-throw (SPDT)
switches. The device is fully specified for ±5 V, +5 V, and +3 V
supplies. The ADG633 switches are turned on with a logic low
(or high) on the appropriate control input. Each switch conducts
equally well in both directions when on and has an input signal
range that extends to the supplies. An EN input is used to enable
or disable the device. When the device is disabled, all channels
are switched off.
The ADG633 is designed on an enhanced process that provides
lower power dissipation, yet is capable of high switching speeds.
Low power consumption and an operating supply range of 2 V
to 12 V make the ADG633 ideal for battery-powered, portable
instruments. All channels exhibit break-before-make switching
action, preventing momentary shorting when switching channels.
FUNCTIONAL BLOCK DIAGRAM
ADG633
S1B
D1
S1A
S3A
D3
S2A S3B
D2
S2B
LOGIC
A0 A1 A2 EN
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 1.
All digital inputs have 0.8 V to 2.4 V logic thresholds, ensuring
TTL/CMOS logic compatibility when using single +5 V or dual
±5 V supplies.
The ADG633 is available in a small, 16-lead TSSOP package
and a 16-lead, 4 mm × 4 mm LFCSP package.
PRODUCT HIGHLIGHTS
1. Single- and dual-supply operation. The ADG633 offers
high performance and is fully specified and guaranteed
with ±5 V, +5 V, and +3 V supply rails.
2. Automotive temperature range: −40°C to +125°C.
3. Guaranteed break-before-make switching action.
4. Low power consumption, typically <0.1 μW.
5. Small, 16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP
packages.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved.
1 page  
ADG633
VDD = 2.7 V to 3.6 V, VSS = 0 V, GND = 0 V, TA = −40°C to +125°C, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match
Between Channels, ΔRON
LEAKAGE CURRENTS
Source Off Leakage, IS(OFF)
Drain Off Leakage, ID(OFF)
Channel On Leakage, ID(ON), IS(ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
+25°C
185
300
2
4.5
±0.005
±0.2
±0.005
±0.2
±0.005
±0.2
0.005
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tBBM
2
170
300
200
310
30
40
180
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS(OFF)
CD(OFF)
CD(ON), CS(ON)
POWER REQUIREMENTS
IDD
1
2
−90
−90
500
5
8
12
0.01
B Version
Y Version
−40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
0 to VDD
V VDD = 2.7 V, VSS = 0 V
Ω typ
VS= 0 V to 2.7 V, IS = 0.1 mA; see Figure 20
350 400
Ω max VS= 0 V to 2.7 V, IS = 0.1 mA; see Figure 20
Ω typ
VS = +1.5 V, IS = 0.1 mA
67
Ω max VS = +1.5 V, IS = 0.1 mA
VDD = 3.3 V
nA typ VS = 1 V/3 V, VD = 3 V/1 V; see Figure 21
±5 nA max VS = 1 V/3 V, VD = 3 V/1 V; see Figure 21
nA typ VS = 1 V/3 V, VD = 3 V/1 V; see Figure 22
±5 nA max VS = 1 V/3 V, VD = 3 V/1 V; see Figure 22
nA typ VS = VD = 1 V or 3 V; see Figure 23
±5 nA max VS = VD = 1 V or 3 V; see Figure 23
2.0 V min
0.5 V max
μA typ
VIN = VINL or VINH
±1 μA max VIN = VINL or VINH
pF typ
370 400
380 420
55 75
10
1
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC max
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
μA typ
μA max
RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 24
RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 24
RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 26
RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 26
RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 26
RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 26
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 1.5 V; see Figure 25
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 1.5 V; see Figure 25
VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27
VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30
RL = 50 Ω, CL = 5 pF; see Figure 29
f = 1 MHz
f = 1 MHz
f = 1 MHz
VDD = 3.3 V
Digital inputs = 0 V or 3.3 V
Digital inputs = 0 V or 3.3 V
1 Guaranteed by design; not subject to production test.
Rev. A | Page 5 of 16
5 Page 
TERMINOLOGY
VDD
Most positive power supply potential.
VSS
Most negative power supply potential.
IDD
Positive supply current.
ISS
Negative supply current.
GND
Ground (0 V) reference.
S
Source terminal. Can be an input or output.
D
Drain terminal. Can be an input or output.
AX
Logic control input.
EN
Active low digital input. When EN is high, the device is disabled
and all switches are off. When EN is low, the Ax logic inputs
determine the on switches.
VD, VS
Analog voltage on Terminal D and Terminal S.
RON
Ohmic resistance between Terminal D and Terminal S.
ΔRON
On-resistance match between any two channels, that is,
RONMAX − RONMIN.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
IS(OFF)
Source leakage current with the switch off.
ID(OFF)
Drain leakage current with the switch off.
ID(ON), IS(ON)
Channel leakage current with the switch on.
VINL
Maximum input voltage for Logic 0.
ADG633
VINH
Minimum input voltage for Logic 1.
IINL, IINH
Input current of the digital input.
CS(OFF)
Off switch source capacitance. Measured with reference to
ground.
CD(OFF)
Off switch drain capacitance. Measured with reference to
ground.
CD(ON), CS(ON)
On switch capacitance. Measured with reference to ground.
CIN
Digital input capacitance.
tON (EN)
Delay between applying the digital control input and the output
switching on (see Figure 26).
tOFF (EN)
Delay between applying the digital control input and the output
switching off (see Figure 26).
tBBM
On time, measured between 80% points of both switches when
switching from one address state to another.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
Rev. A | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADG633.PDF ] | |
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