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R5F5630 Schematic ( PDF Datasheet ) - Renesas

Teilenummer R5F5630
Beschreibung MCUs
Hersteller Renesas
Logo Renesas Logo 




Gesamt 30 Seiten
R5F5630 Datasheet, Funktion
Features
DATASHEET
RX630 Group
Renesas MCUs
R01DS0060EJ0160
Rev.1.60
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS,
May 19, 2014
up to 2-MB flash memory, USB 2.0 full-speed function interface,
CAN, 10- & 12-bit A/D converter, RTC, up to 22 comms interfaces
Features
32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories
and between registers)
32-bit multiplier (fastest instruction execution takes one CPU
clock cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
Two types of debugging interfaces: JTAG and FINE (two-line)
Low-power design and architecture
Operation from a single 2.7- to 3.6-V supply
Low power consumption: A product that supports all peripheral
functions draws only 500 μA/MHz.
RTC is capable of operation from a dedicated power supply (min.
operating voltage: 2.3 V).
Four low-power modes
On-chip main flash memory, no wait states
100-MHz operation, 10-ns read cycle (no wait states)
384-Kbyte to 2-Mbyte capacities
User code is programmable by on-board or off-board
programming.
On-chip data flash memory
Max. 32 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
On-chip SRAM, no wait states
32- to 128-Kbyte capacities
For instructions and operands
Can provide backup on deep software standby
DMA
DMAC: Incorporates four channels
DTC
Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
External crystal oscillator or internal PLL for operation at 4 to 16
MHz
Internal 125-kHz LOCO and 50-MHz HOCO
125-kHz clock for the IWDT
Frequency of the oscillator for sub-clock generation: 32 kHz
Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Time capture function
(for capturing times in response to event-signal input on external
pins)
Independent watchdog timer
125-kHz LOCO clock operation
Useful functions for IEC60730 compliance
Oscillation-stop detection, frequency measurement, CRC, IWDT,
self-diagnostic function for the A/D converter, etc.
PLQP0176KB-A 24 × 24 mm, 0.5-mm pitch
PLQP0144KA-A 20 × 20 mm, 0.5-mm pitch
PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch
PLQP0080KB-A 12 × 12 mm, 0.5-mm pitch
PTLG0177JB-A 8 × 8 mm, 0.5-mm pitch
PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch
PTLG0100KA-A 5.5 × 5.5 mm, 0.5-mm pitch
PLBG0176GA-A 13 × 13 mm, 0.8-mm pitch
Up to 22 communications interfaces
USB 2.0 full-speed function interface (1 channel)
CAN (compliant with ISO11898-1), incorporating 32 mailboxes
(up to 3 channels)
SCI with multiple functionalities (up to 13 channels)
Choose from among asynchronous mode, clock-synchronous
mode, smart-card interface mode, simple SPI, simple I2C, and
extended serial mode.
I2C bus interface for transfer at up to 1 Mbps (up to 4 channels)
RSPI for high-speed transfer (up to 3 channels)
External address space
8 CS areas (8 × 16 Mbytes)
Multiplexed address data or separate address lines are selectable
per area.
8-, 16-, or 32-bit bus space is selectable per area
Up to 20 extended-function timers
16-bit MTU2: input capture, output capture, complementary PWM
output, phase-counting mode (6 channels)
16-bit TPU: input capture, output capture, phase-counting mode
(12 channels)
8-bit TMR (4 channels)
16-bit compare-match timers (4 channels)
A/D converter for 1-MHz operation
Up to 21 12-bit channels, and incorporating 1 sample-and-hold
circuit
Up to 8 10-bit channels, and incorporating 1 sample-and-hold
circuit
Addition of results of A/D conversion (in the 12-bit A/D converter)
self-diagnosis (for the 10-bit A/D converter)
10-bit D/A converter: 2 channels
Temperature sensor for measuring temperature
within the chip
Register write protection function can protect
values in important registers against overwriting.
Up to 148 general I/O port pins for GPIO
5-V tolerance, open drain, input pull-up, switchable driving ability
Unique ID
16-byte ID code is provided for each chip (only for the G version)
Operating temp. range
D version: -40 to +85°C
G version: -40 to +105°C
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 1 of 154






R5F5630 Datasheet, Funktion
RX630 Group
1. Overview
Table 1.1
Outline of Specifications (5/5)
Classification Module/Function
Description
10-bit A/D converter (ADb)
1 unit (1 unit × 8 channels)
10-bit resolution
Conversion time: 1.0 µs per channel (in operation with PCLK at 50 MHz)
Operating mode
Scan mode (single scan mode or continuous scan mode)
External amplifier connection mode
Sample-and-hold function
Three ways to start A/D conversion
Conversion can be started by software, a conversion start trigger from a timer (MTU,
TPU, or TMR), or an external trigger signal.
D/A converter (DAa)
2 channels
10-bit resolution
Output voltage: 0 V to VREFH
Temperature sensor
1 channel
Precision: ± 1 ºC
The voltage of the temperature is converted into a digital value by the 12-bit A/D
converter.
CRC calculator (CRC)
CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1.
Generation of CRC codes for use with LSB-first or MSB-first communications is
selectable
Unique ID
A 16-byte device-specific ID (only for the G version)
Operating frequency
Up to 100 MHz
Power supply voltage
VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, Vbatt =
2.3 to 3.6 V
Operating temperature
D version: -40 to +85°C,
G version: -40 to +105°C*1
Package
177-pin TFLGA (PTLG0177KA-A) (in planning)
176-pin LFBGA (PLBG0176GA-A) (in planning)
176-pin LQFP (PLQP0176KB-A)
145-pin TFLGA (PTLG0145KA-A) (in planning)
144-pin LQFP (PLQP0144KA-A)
100-pin TFLGA (PTLG0100KA-A) (in planning)
100-pin LQFP (PLQP0100KB-A)
80-pin LQFP (PLQP0080KB-A) (in planning)
On-chip debugging system
E1 emulator (JTAG and FINE interfaces)
E20 emulator (JTAG interface)
Note 1. Please contact us if you are using a G version.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 6 of 154

6 Page









R5F5630 pdf, datenblatt
RX630 Group
1. Overview
1.4 Pin Functions
Table 1.4 lists the pin functions.
Table 1.4
Pin Functions (1/5)
Classifications
Pin Name
Power supply
VCC
VCL
VSS
VBATT
Clock
Operating mode control
XTAL
EXTAL
BCLK
XCOUT
XCIN
MD
System control
RES#
EMLE
On-chip emulator
Address bus
Data bus
Multiplexed bus
BSCANP
FINEC
FINED
TRST#
TMS
TDI
TCK
TDO
TRCLK
TRSYNC
TRDATA0 to TRDATA3
A0 to A23
D0 to D31
A0/D0 to A15/D15
I/O
Input
Input
Input
Input
Output
Input
Output
Output
Input
Input
Input
Input
Input
Input
I/O
Input
Input
Input
Input
Output
Output
Output
Output
Output
I/O
I/O
Description
Power supply pin. Connect it to the system power supply. Connect
this pin to VSS via a 0.1-µF capacitor. The capacitor should be
placed close to the pin
Connect this pin to VSS via a 0.1-F capacitor. The capacitor
should be placed close to the pin
Ground pin. Connect it to the system power supply (0 V)
Backup power pin. When the battery backup function is not to be
used, connect it to the VCC pin.
Pins for a crystal resonator. An external clock signal can be input
through the EXTAL pin
Outputs the external bus clock for external devices
Input/output pins for the sub-clock oscillator circuit. Connect a
crystal resonator between XCOUT and XCIN
Pin for setting the operating mode. The signal levels on these pins
must not be changed during operation
Reset signal input pin. This LSI enters the reset state when this
signal goes low
Input pin for the on-chip emulator enable signal. When the on-chip
emulator is used, this pin should be driven high. When not used, it
should be driven low
Boundary scan enable pin. Boundary scan is enabled when this pin
goes high. When not used, it should be driven low
Fine interface clock pin
Fine interface pin
On-chip emulator or boundary scan pins. When the EMLE pin is
driven high, these pins are dedicated for the on-chip emulator
This pin outputs the clock for synchronization with the trace data
This pin indicates that output from the TRDATA0 to TRDATA3 pins
is valid
These pins output the trace information
Output pins for the address
Input and output pins for the bidirectional data bus
Address/data multiplexed bus
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 12 of 154

12 Page





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