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R5F521A6BDFN Schematic ( PDF Datasheet ) - Renesas

Teilenummer R5F521A6BDFN
Beschreibung MCUs
Hersteller Renesas
Logo Renesas Logo 




Gesamt 30 Seiten
R5F521A6BDFN Datasheet, Funktion
Datasheet
RX21A Group
Renesas MCUs
50-MHz 32-bit RX MCUs, 78 DMIPS, 24-bit ∆Σ A/D Converter,
up to 512-KB flash memory, IrDA, 10-bit A/D, 10-bit D/A, DEU, ELC,
MPC, RTC; up to 9 comms interfaces
R01DS0129EJ0110
Rev.1.10
Aug 28, 2014
Features
32-bit RX CPU core
Max. operating frequency: 50 MHz
Capable of 78 DMIPS in operation at 50 MHz
Accumulator handles 64-bit results (for a single
instruction) from 32- × 32-bit operations
Multiplication and division unit handles 32- × 32-bit
operations (multiplication instructions take one CPU
clock cycle)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions, ultra-compact code
Memory protection unit
On-chip debugging circuit
Low power design and architecture
Operation from a single 1.8-V to 3.6-V supply
(2.7 V to 3.6 V for the ΔΣ A/D converter operating
voltage)
Deep software standby mode with RTC remaining usable
Four low power modes
24-bit ∆Σ A/D Converter
SNDR = 85dB
Seven ΔΣ converter units available. Seven channels can
be operated simultaneously or independently.
Up to x 64 PGA gain for differential input
On-chip flash memory for code, no wait states
50-MHz operation, 20-ns read cycle
No wait states for reading at full CPU speed
256-K to 512-Kbyte capacities
User code programmable via the SCI
Programmable at 1.8 V
For instructions and operands
On-chip data flash memory
8 Kbytes
(Number of times of reprogramming: 100,000)
Erasing and programming impose no load on the CPU.
On-chip SRAM, no wait states
32-K to 64-Kbyte size capacities
DMA
DMAC: Incorporates four channels
DTC: Four transfer modes
Reset and supply management
Nine types of reset, including the power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
Frequency of external clock: Up to 20 MHz
Frequency of the oscillator for sub-clock generation:
32.768 kHz
PLL circuit input: 4 MHz to 12.5 MHz
On-chip low- and high-speed oscillators, dedicated on-
chip low-speed oscillator for the IWDT
Generation of a dedicated 32.768-kHz clock for the RTC
Clock frequency accuracy measurement circuit (CAC)
Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Year and month display or 32-bit second display (binary
counter) is selectable
Time capture on event-signal input through external pins
RTC capable of initiating return from deep software
standby mode
PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch
PLQP0080KB-A 12 × 12 mm, 0.5-mm pitch
PLQP0064KB-A 10 × 10 mm, 0.5-mm pitch
PTLG0100JA-A 7×7mm, 0.65-mm pitch
Independent watchdog timer
125-kHz on-chip oscillator produces a dedicated clock
signal to drive IWDT operation.
Useful functions for IEC60730 compliance
Self-diagnostic and disconnection-detection assistance
functions for the A/D converter, clock-frequency
accuracy-measurement circuit, independent watchdog
timer, functions to assist in RAM testing, etc.
Up to nine communications channels
SCI with many useful functions (up to five channels)
Asynchronous mode, clock synchronous mode, smart
card interface
IrDA Interface (one channel, in cooperation with the
SCI5)
I2C bus interface: Transfer at up to 400 kbps, capable of
SMBus operation (two channels)
RSPI (two channels)
Up to 14 extended-function timers
16-bit MTU: input capture, output compare,
complementary PWM output, phase counting mode
(six channels)
8-bit TMR (four channels)
16-bit compare-match timers (four channels)
10-bit A/D converter
Conversion time 2.0 μs
Self-diagnostic function and analog input disconnection
detection assistance function
10-bit D/A converter
Analog comparator
General I/O ports
5-V tolerant, open drain, input pull-up, switching of
driving ability
MPC
Multiple locations are selectable for I/O pins of
peripheral functions
ELC
Module operation can be initiated by event signals
without going through interrupts.
Modules can operate while the CPU is sleeping.
DEU
Encryption and decryption of AES
128-, 192-, or 256-bit key length
ECB/CBC Mode
Temperature sensor
Operating temp. range
 40C to +85C
 40C to +105C
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 1 of 132






R5F521A6BDFN Datasheet, Funktion
RX21A Group
1. Overview
1.2 List of Products
Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no., memory capacity, and package
type.
Table 1.3
List of Products
Group
RX21A
Part No.
R5F521A8BDFP
R5F521A8BDFN
R5F521A8BDFM
R5F521A8BDLJ
R5F521A7BDFP
R5F521A7BDFN
R5F521A7BDFM
R5F521A7BDLJ
R5F521A6BDFP
R5F521A6BDFN
R5F521A6BDFM
R5F521A6BDLJ
R5F521A8BGFP
R5F521A8BGFN
R5F521A8BGFM
R5F521A7BGFP
R5F521A7BGFN
R5F521A7BGFM
R5F521A6BGFP
R5F521A6BGFN
R5F521A6BGFM
Package
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PTLG0100JA-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PTLG0100JA-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PTLG0100JA-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
ROM
Capacity
RAM
Capacity
E2
Operating
Operating
DataFlash Frequency (Max.) temperature
512 Kbytes
64 Kbytes
384 Kbytes
8 Kbytes
50 MHz
40 to +85°C
256 Kbytes 32 Kbytes
512 Kbytes
64 Kbytes
384 Kbytes
8 Kbytes
50 MHz
256 Kbytes 32 Kbytes
40 to +105°C
*1, *2
Note: • Orderable part numbers are current as of when this manual was published. Please make sure to refer to the relevant product
page on the Renesas website for the latest part numbers.
Note 1. Please contact Renesas Electronics sales office for derating of operation under Ta = +85°C to +105°C. Derating is the
systematic reduction of load for the sake of improved reliability.
Note 2. The unique ID specification and the calibration functions of the temperature sensor and the 24-Bit ∆Σ A/D converter of these
products differ from other products. For details, see following sections in the RX21A Group User’s Manual: Hardware.
section 34.2.11, ∆Σ A/D Input Impedance Calibration Data Register (DSADIIC)
section 34.2.12, ∆Σ A/D Gain Calibration Data Registers (DSADGmXn) (m = 0 to 6, n = 1, 2, 4, 8, 16, and 32)
section 37.2.2, Temperature Sensor Calibration Data Registers (TSCDRn) (n = 0,1,3)
section 37.3, Using the Temperature Sensor
section 42.2.15, Unique ID Registers (UIDRn) (n = 0 to 3)
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 6 of 132

6 Page









R5F521A6BDFN pdf, datenblatt
RX21A Group
1. Overview
1.5 Pin Assignments
Figure 1.3 to Figure 1.5 show the pin assignments. Table 1.5 to Table 1.7 show the lists of pins and pin functions.
ANDS1N
ANDS1P
ANDS2N
ANDS2P
ANDS3N
ANDS3P
AVSSA
AVCCA
VREFDSL
VREFDSH
VCOMDS
ANDS4
ANDS5
ANDS6
ANDSSG
P43
P42
P41
VREFL0
P40
VREFH0
AVCC0
P07
AVSS0
P05
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
RX21A Group
PLQP0100KB-A
(100-pin LQFP)
(Top view)
50 PC2
49 PC3
48 PC4
47 PC5
46 PC6
45 PC7
44 P50
43 P51
42 P52
41 P53
40 P54
39 P55
38 PH0
37 PH1
36 PH2
35 PH3
34 P12
33 P13
32 P14
31 P15
30 P16
29 P17
28 P20
27 P21
26 P22
Figure 1.3
Note: • This figure indicates the power supply pins and I/O port pins. For the pin
configuration, see the table “List of Pins and Pin Functions (100-Pin LQFP)”.
Pin Assignments of the 100-Pin LQFP
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 12 of 132

12 Page





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