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ADG5436F Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADG5436F
Beschreibung Dual SPDT Switch
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADG5436F Datasheet, Funktion
Data Sheet
Fault Protection and Detection,
10 Ω RON, Dual SPDT Switch
ADG5436F
FEATURES
Overvoltage protection up to −55 V and +55 V
Power-off protection up to −55 V and +55 V
Overvoltage detection on source pins
Interrupt flags indicate fault status
Low on resistance: 10 Ω (typical)
On-resistance flatness of 0.5 Ω (maximum)
6 kV human body model (HBM) ESD rating
Latch-up immune under any circumstance
Known state without digital inputs present
VSS to VDD analog signal range
±5 V to ±22 V dual supply operation
8 V to 44 V single-supply operation
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
APPLICATIONS
Analog input/output modules
Process control/distributed control systems
Data acquisition
Instrumentation
Avionics
Automatic test equipment
Communication systems
Relay replacement
GENERAL DESCRIPTION
The ADG5436F is an analog multiplexer, containing two
independently selectable single-pole, double-throw (SPDT)
switches. An EN input is used to disable all the switches. For use
in multiplexer applications, both switches exhibit break-before-
make switching action.
Each channel conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
supplies. The digital inputs are compatible with 3 V logic inputs
over the full operating supply range.
When no power supplies are present, the switch remains in the off
condition, and the channel inputs are high impedance. Under
normal operating conditions, if the analog input signal level on
any Sxx pin exceeds VDD or VSS by a threshold voltage, VT, the
channel turns off and that Sxx pin becomes high impedance. If
the channel is on, the drain pin reacts according to the drain
response (DR) input pin. If the DR pin is left floating or pulled
high, the drain remains high impedance and floats. If the DR pin
is pulled low, the drain pulls to the exceeded rail. Input signal
levels of up to +55 V or −55 V relative to ground are blocked, in
both the powered and unpowered conditions. The low on
Rev. B
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
ADG5436F
S1A
D1
S1B
S2A
D2
S2B
FAULT
DETECTION
+
SWITCH DRIVER
SF
FF
IN1 IN2 EN DR
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 1.
resistance of the ADG5436F, combined with the on-resistance
flatness over a significant portion of the signal range, makes it
an ideal solution for data acquisition and gain switching
applications where excellent linearity and low distortion are
critical.
Note that, throughout this data sheet, the dual function pin names
are referenced only by the relevant function where applicable. See
the Pin Configurations and Function Descriptions section for
full pin names and function descriptions.
PRODUCT HIGHLIGHTS
1. Source pins are protected against voltages greater than the
supply rails, up to −55 V and +55 V.
2. Source pins are protected against voltages between −55 V
and +55 V in an unpowered state.
3. Overvoltage detection with digital output indicates the
operating state of the switches.
4. Trench isolation guards against latch-up.
5. Optimized for low on resistance and on-resistance flatness.
6. The ADG5436F operates from a dual supply of ±5 V up to
±22 V, or a single power supply of 8 V up to 44 V.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADG5436F Datasheet, Funktion
ADG5436F
Data Sheet
Parameter
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−3 dB Bandwidth
Insertion Loss
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IGND
ISS
Fault Mode
IDD
IGND
ISS
VDD/VSS
1 Guaranteed by design. Not subject to production test.
−40°C to −40°C to
+25°C +85°C
+125°C Unit
Test Conditions/Comments
405
540
430
535
170
205
330
430
560
930
1300
85
60
600
−737
−72
−73
0.001
171
−0.8
11
23
36
555
560
210
605
1500
0.9
1.2
0.4
0.55
0.5
0.65
1.2
1.6
0.8
1.0
0.5
1.0
570
585
215
205
630
1700
115
85
1.3
0.6
0.7
1.8
1.1
1.8
±5
±22
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
dB typ
dB typ
% typ
MHz typ
dB typ
pF typ
pF typ
pF typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 46
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 45
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 45
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 44
RL = 1 kΩ, CL = 2 pF, see Figure 39
RL = 1 kΩ, CL = 2 pF, see Figure 40
CL = 12 pF, see Figure 41
CL = 12 pF, see Figure 42
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 43
VS = 0 V, RS = 0 Ω, CL = 1 nF, see
Figure 47
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 34
RL = 10 kΩ, VS = 20 V p-p, f = 20 Hz to
20 kHz, see Figure 38
RL = 50 Ω, CL = 5 pF, see Figure 37
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 37
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = 22 V, VSS = −22 V, digital inputs =
0 V, 5 V, or VDD
mA typ
mA max
mA typ
mA max
mA typ
mA max
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
V max
VS = ±55 V
Digital inputs = 5 V
VS = ±55 V, VD = 0 V
GND = 0 V
GND = 0 V
Rev. B | Page 6 of 30

6 Page









ADG5436F pdf, datenblatt
ADG5436F
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Sxx to GND
Sxx to VDD or VSS
VS to VD
Dx Pin1 to GND
Digital Inputs to GND
Peak Current, Sxx or Dx Pins
Continuous Current, Sxx or Dx
Digital Output
Dx Pin, Overvoltage State,
DR = GND, Load Current
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Thermal Impedance, θJA
16-Lead TSSOP (4-Layer Board)
16-Lead LFCSP (4-Layer Board)
Reflow Soldering Peak
Temperature, Pb-Free
ESD Rating, HBM: ESDA/JEDEC
JS-001-2011
Input/Output (I/O) Port to
Supplies
I/O Port to I/O Port
All Other Pins
Rating
48 V
−0.3 V to +48 V
−48 V to +0.3 V
−55 V to +55 V
80 V
80 V
VSS − 0.7 V to VDD + 0.7 V or
30 mA, whichever occurs first
GND − 0.7 V to 48 V or
30 mA, whichever occurs first
288 mA (pulsed at 1 ms,
10% duty cycle maximum)
Data2 + 15%
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
1 mA
−40°C to +125°C
−65°C to +150°C
150°C
112.6°C/W
30.4°C/W
As per JEDEC J-STD-020
6 kV
6 kV
6 kV
1 Overvoltages at the Dx pin are clamped by internal diodes. Limit current to
the maximum ratings given.
2 See Table 5.
Data Sheet
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
Rev. B | Page 12 of 30

12 Page





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