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W971GG8KB Schematic ( PDF Datasheet ) - Winbond

Teilenummer W971GG8KB
Beschreibung 16M x 8-BANKS x 8-BIT DDR2 SDRAM
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W971GG8KB Datasheet, Funktion
W971GG8KB
16M 8 BANKS 8 BIT DDR2 SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ...................................................................................................................4
2. FEATURES ...........................................................................................................................................4
3. ORDER INFORMATION .......................................................................................................................4
4. KEY PARAMETERS .............................................................................................................................5
5. BALL CONFIGURATION ......................................................................................................................6
6. BALL DESCRIPTION............................................................................................................................7
7. BLOCK DIAGRAM ................................................................................................................................8
8. FUNCTIONAL DESCRIPTION..............................................................................................................9
8.1 Power-up and Initialization Sequence ...................................................................................................9
8.2 Mode Register and Extended Mode Registers Operation ...................................................................10
8.2.1
Mode Register Set Command (MRS)...............................................................................10
8.2.2
Extend Mode Register Set Commands (EMRS) ..............................................................11
8.2.2.1
Extend Mode Register Set Command (1), EMR (1)................................................11
8.2.2.2
DLL Enable/Disable................................................................................................12
8.2.2.3
Extend Mode Register Set Command (2), EMR (2)................................................13
8.2.2.4
Extend Mode Register Set Command (3), EMR (3)................................................14
8.2.3
Off-Chip Driver (OCD) Impedance Adjustment ................................................................15
8.2.3.1
Extended Mode Register for OCD Impedance Adjustment ....................................16
8.2.3.2
OCD Impedance Adjust ..........................................................................................16
8.2.3.3
Drive Mode .............................................................................................................17
8.2.4
On-Die Termination (ODT)...............................................................................................18
8.2.5
ODT related timings .........................................................................................................18
8.2.5.1
MRS command to ODT update delay.....................................................................18
8.3 Command Function.............................................................................................................................20
8.3.1
Bank Activate Command..................................................................................................20
8.3.2
Read Command ...............................................................................................................21
8.3.3
Write Command ...............................................................................................................21
8.3.4
Burst Read with Auto-precharge Command.....................................................................21
8.3.5
Burst Write with Auto-precharge Command.....................................................................21
8.3.6
Precharge All Command ..................................................................................................21
8.3.7
Self Refresh Entry Command ..........................................................................................21
8.3.8
Self Refresh Exit Command .............................................................................................22
8.3.9
Refresh Command ...........................................................................................................22
8.3.10
No-Operation Command ..................................................................................................23
8.3.11
Device Deselect Command..............................................................................................23
8.4 Read and Write access modes ...........................................................................................................23
8.4.1
Posted CAS ....................................................................................................................23
Publication Release Date: Sep. 11, 2013
- 1 - Revision A02






W971GG8KB Datasheet, Funktion
W971GG8KB
5. BALL CONFIGURATION
123456789
VDD NU/RDQS VSS
DQ6 VSSQ DM/RDQS
VDDQ DQ1 VDDQ
DQ4 VSSQ DQ3
VDDL VREF VSS
CKE WE
BA2 BA0 BA1
A10/AP A1
VSS A3
A5
A7 A9
VDD A12 NC
A
B
C
D
E
F
G
H
J
K
L
VSSQ DQS VDDQ
DQS VSSQ DQ7
VDDQ DQ0 VDDQ
DQ2 VSSQ DQ5
VSSDL CLK VDD
RAS CLK ODT
CAS CS
A2 A0 VDD
A6 A4
A11 A8 VSS
NC A13
Publication Release Date: Sep. 11, 2013
- 6 - Revision A02

6 Page









W971GG8KB pdf, datenblatt
W971GG8KB
8.2.2.2 DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization,
and upon returning to normal operation after having the DLL disabled. The DLL is automatically
disabled when entering Self Refresh operation and is automatically re-enabled and reset upon exit of
Self Refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must
occur before a Read command can be issued to allow time for the internal clock to be synchronized
with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC
or tDQSCK parameters.
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Field
0 0 1 0 Qoff RDQS DQS
OCD program
Rtt
AdditiveWLRatencyBT Rtt D.I.C DLL Extended Mode Register (1)
BA1
0
0
1
1
BA0
0
1
0
1
MRS mode
MRS
EMR (1)
EMR (2)
EMR (3)
A6 A2
00
01
10
11
Driver impedance adjustment
A9 A8 A7
OCD Calibration Program
000
OCD calibration mode exit; matain setting
001
Drive (1)
010
100
111
Drive (0)
Adjust mode*2
OCD Calibration default*3
A12 Qoff
0 Output duffers enabled
1 Output duffers disabled
A10 DQS
0 Enable
1 Disable
A11 RDQS Enable*4
0 Disable
1 Enable
A11
(RDQS Enable)
0 (Disable)
0 (Disable)
1 (Enable)
1 (Enable)
A10
(DQS Enable)
0 (Enable)
1 (Disable)
0 (Enable)
1 (Disable)
Rtt (nominal)
ODT disabled
75 ohm
150 ohm
50 ohm*1
A0 DLL Enable
0 Enable
1 Disable
Driver strength control
A1
Output driver
impedance control
Driver size
0 Normal
1 Reduced
100%
60%
Additive Latency
A5 A4 A3
Latency
000
0
001
1
010
2
011
3
100
4
101
5
110
6
1 1 1 Resesved
RDQS/DM
DM
DM
RDQS
RDQS
Strobe Function Matrix
RDQS
Hi-z
DQS
DQS
Hi-z DQS
RDQS
DQS
Hi-z DQS
DQS
DQS
Hi-z
DQS
Hi-z
Notes:
1. Optional for DDR2-667, mandatory for DDR2-800 and DDR2-1066.
2. When Adjust mode is issued, AL from previously set value must be applied.
3. After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000. Refer to the section 8.2.3 for
detailed information.
4. If RDQS is enabled, the DM function is disabled. RDQS is active for reads and don‟t care for writes.
Figure 3 EMR (1)
- 12 -
Publication Release Date: Sep. 11, 2013
Revision A02

12 Page





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