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W9816G6IH Schematic ( PDF Datasheet ) - Winbond

Teilenummer W9816G6IH
Beschreibung 512K x 2-BANKS x 16-BITS SDRAM
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W9816G6IH Datasheet, Funktion
W9816G6IH
512K × 2 BANKS × 16 BITS SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. AVAILABLE PART NUMBER ..................................................................................................... 3
4. PIN CONFIGURATION ............................................................................................................... 4
5. PIN DESCRIPTION..................................................................................................................... 5
6. BLOCK DIAGRAM ...................................................................................................................... 6
7. FUNCTIONAL DESCRIPTION ................................................................................................... 7
7.1 Power Up and Initialization ............................................................................................. 7
7.2 Programming Mode Register.......................................................................................... 7
7.3 Bank Activate Command ................................................................................................ 7
7.4 Read and Write Access Modes ...................................................................................... 7
7.5 Burst Read Command .................................................................................................... 8
7.6 Burst Write Command .................................................................................................... 8
7.7 Read Interrupted by a Read ........................................................................................... 8
7.8 Read Interrupted by a Write............................................................................................ 8
7.9 Write Interrupted by a Write............................................................................................ 8
7.10 Write Interrupted by a Read............................................................................................ 8
7.11 Burst Stop Command ..................................................................................................... 9
7.12 Addressing Sequence of Sequential Mode .................................................................... 9
7.13 Addressing Sequence of Interleave Mode ..................................................................... 9
7.14 Auto-precharge Command ........................................................................................... 10
7.15 Precharge Command.................................................................................................... 10
7.16 Self Refresh Command ................................................................................................ 10
7.17 Power Down Mode ....................................................................................................... 11
7.18 No Operation Command............................................................................................... 11
7.19 Deselect Command ...................................................................................................... 11
7.20 Clock Suspend Mode.................................................................................................... 11
8. OPERATION MODE ................................................................................................................. 12
9. ELECTRICAL CHARACTERISTICS......................................................................................... 13
9.1 Absolute Maximum Ratings .......................................................................................... 13
9.2 Recommended DC Operating Conditions .................................................................... 13
Publication Release Date: Mar. 22, 2010
- 1 - Revision A02






W9816G6IH Datasheet, Funktion
6. BLOCK DIAGRAM
W9816G6IH
CLK
CKE
CLOCK
BUFFER
CS
RAS
CAS
WE
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
A10
MODE
A0 REGISTER
A9
BA
ADDRESS
BUFFER
COLUMN DECODER
R
O
W CELL ARRAY
D
E
BANK #0
C
O
D
E
R
SENSE AMPLIFIER
DATA CONTROL
CIRCUIT
DQ
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
COLUMN DECODER
R
O
W
D CELL ARRAY
E
C
BANK #1
O
D
E
R
SENSE AMPLIFIER
Note: The cell array configuration is 2048 * 256 * 16
DQ0
DQ15
LDQM
UDQM
Publication Release Date: Mar. 22, 2010
- 6 - Revision A02

6 Page









W9816G6IH pdf, datenblatt
W9816G6IH
8. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
TABLE 1 TRUTH TABLE (NOTE 1, 2)
COMMAND
DEVICE
STATE
CKEn-1 CKEn DQM BA A10 A9-A0 CS RAS CAS
Bank Active
Idle H X X V V V L L H
Bank Precharge
Any H X X V L X L L H
Precharge All
Write
Write with Auto-precharge
Read
Read with Auto-precharge
Any
Active (3)
Active (3)
Active (3)
Active (3)
H X XXH X L LH
H X XVL V LHL
H X XVH V LHL
H X XVL V LHL
H X XVH V LHL
Mode Register Set
Idle H X X V V V L L L
No-Operation
Burst Stop
Any
Active (4)
H X XXX X LHH
H X XXX X LHH
Device Deselect
Any H X X X X X H X X
Auto-Refresh
Idle H H X X X X L L L
Self-Refresh Entry
Idle H L X X X X L L L
Self-Refresh Exit
Idle
(S.R)
L H XXX X HXX
L H XXX X LHH
Clock Suspend Mode
Entry
Active
H L XXX X XXX
Power Down Mode Entry
Idle
Active (5)
H L XXX X HXX
H L XXX X LHH
Clock Suspend Mode Exit
Active
L H XXX X XXX
Power Down Mode Exit
Any
(power down)
L
L
H XXX X HXX
H XXX X LHH
Data Write/Output Enable
Active
H X LXX X XXX
Data Write/Output Disable
Active
H
X HXX X XXX
WE
H
L
L
L
L
H
H
L
H
L
X
H
H
X
X
X
X
X
X
X
X
X
X
Notes(1) V = Valid, X = Don't care, L = Low Level, H = High Level
(2) CKEn signal is input level when commands are provided.
CKEn-1 signal is the input level one clock cycle before the command is issued.
(3) These are state of bank designated by BA signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
- 12 -
Publication Release Date: Mar. 22, 2010
Revision A02

12 Page





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