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R1EX25512ASA00A Schematic ( PDF Datasheet ) - Renesas

Teilenummer R1EX25512ASA00A
Beschreibung 512k EEPROM
Hersteller Renesas
Logo Renesas Logo 




Gesamt 22 Seiten
R1EX25512ASA00A Datasheet, Funktion
R1EX25512ASA00A
R1EX25512ATA00A
Serial Peripheral Interface
512K EEPROM (64-Kword × 8-bit)
Preliminary Datasheet
R10DS0046EJ0200
Rev.2.00
Oct.04, 2010
Description
R1EX25xxx series is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and
Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing
advanced MONOS memory technology and CMOS process and low voltage circuitry technology. They also have a
128-byte page programming function to make their write operation faster.
Note: Renesas Electronics' serial EEPROMs are authorized for using consumer applications such as cellular phones,
camcorders and audio equipments. Therefore, please contact Renesas Electronics' sales office before using
industrial applications such as automotive systems, embedded controllers and meters.
Features
Single supply: 1.8 V to 5.5 V
Serial Peripheral Interface compatible (SPI bus)
SPI mode 0 (0,0), 3 (1,1)
Clock frequency: 5 MHz (2.5 V to 5.5 V), 3 MHz (1.8 V to 5.5 V)
Power dissipation:
Standby: 5 µA (max)
Active (Read): 5 mA (max)
Active (Write): 5 mA (max)
Automatic page write: 128-byte/page
Write cycle time: 5 ms (max)
Endurance: 1,000k Cycles @25 °C
Data retention: 100 Years @25 °C
Small size packages: SOP-8pin, TSSOP-8pin
Shipping tape and reel
TSSOP-8pin : 3,000 IC/reel
SOP-8pin : 2,500 IC/reel
Temperature range: 40 to +85°C
Lead free product.
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
Page 1 of 20






R1EX25512ASA00A Datasheet, Funktion
R1EX25512ASA00A/R1EX25512ATA00A
Parameter
Clock frequency
S active setup time
S not active setup time
S deselect time
S active hold time
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock high setup time before HOLD active
Clock high setup time before HOLD not
active
Output disable time
Clock low to output valid
Output hold time
Output rise time
Output fall time
HOLD high to output low-Z
HOLD low to output low-Z
Write time
Notes: 1. tCH + tCL 1/fC
2. Not 100% tested
Symbol
fC
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCH
tCL
tCLCH
tCHCL
tDVCH
tCHDX
tHHCH
tHLCH
tCHHL
tCHHH
tSHQZ
tCLQV
tCLQX
tQLQH
tQHQL
tHHQX
tHLQZ
tW
Alt
fSCK
tCSS1
tCSS2
tCS
tCSH
tCLH
tCLL
tRC
tFC
tDSU
tDH
tDIS
tV
tHO
tRO
tFO
tLZ
tHZ
tWC
(Ta = 40 to +85°C, VCC = 1.8 V to 5.5 V)
Min Max Unit Notes
3 MHz
100
ns
100
ns
250
ns
100
ns
100
ns
150
ns
1
150
ns
1
1 µs 2
1 µs 2
30 ns
50 ns
200
ns
200
ns
120
ns
120
ns
200 ns
150 ns
0 ns
100 ns
100 ns
100 ns
100 ns
5 ms
2
2
2
2
2
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
Page 6 of 20

6 Page









R1EX25512ASA00A pdf, datenblatt
R1EX25512ASA00A/R1EX25512ATA00A
Read Status Register (RDSR):
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at
any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is
recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also
possible to read the Status Register continuously, as shown in the following figure.
Read Status Register (RDSR) Sequence
VIH
S VIL
VIH
W VIL
C VIH
VIL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D VIH
VIL
Q
High-Z
Status Register Out
7 6 5 4 32 1 07
The status and control bits of the Status Register are as follows:
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register
cycle. When set to 1, such a cycle is in progress. When reset to 0, no such cycles are in progress.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1, the
internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no Write or Write Status
Register instructions are accepted.
BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When
one or both of the Block Protect (BP1, BP0) bits are set to 1, the relevant memory area (as defined in the Write Protect
Block Size table) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be
written provided that the Hardware Protected mode has not been set.
SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the write protect (W) signal.
The Status Register Write Disable (SRWD) bit and write protect (W) signal allows the device to be put in the Hardware
Protected mode (When the Status Register Write Disable (SRWD) bit is set to 1, and write protect (W) signal is driven
low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write
Status Register (WRSR) instruction is no longer accepted for execution.
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
Page 12 of 20

12 Page





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