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R5F2136CANFP Schematic ( PDF Datasheet ) - Renesas

Teilenummer R5F2136CANFP
Beschreibung MCU
Hersteller Renesas
Logo Renesas Logo 




Gesamt 30 Seiten
R5F2136CANFP Datasheet, Funktion
R8C/36A Group
RENESAS MCU
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
REJ03B0265-0110
Rev.1.10
Sep 28, 2009
1. Overview
1.1 Features
The R8C/36A Group of single-chip MCUs incorporate the R8C CPU core, employing sophisticated instructions for
a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high speed.
In addition, the CPU core boasts a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
The R8C/36A Group have data flash (1 KB × 4 blocks) with the background operation (BGO) function.
1.1.1 Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009
Page 1 of 55






R5F2136CANFP Datasheet, Funktion
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/36A Group
1. Overview
1.4 Pin Assignment
Figure 1.3 shows Pin Assignment (Top View). Tables 1.4 and 1.5 outline the Pin Name Information by Pin
Number.
P0_7/AN0/DA1(/TRCIOC)
P0_6/AN1/DA0(/TRCIOD)
P0_5/AN2(/TRCIOB)
P0_4/AN3/TREO(/TRCIOB)
P0_3/AN4(/CLK1/TRCIOB)
P0_2/AN5(/RXD1/TRCIOA/TRCTRG)
P0_1/AN6(/TXD1/TRCIOA/TRCTRG)
P0_0/AN7(/TRCIOA/TRCTRG)
P6_4(/RXD1)
P6_3(/TXD1)
P6_2(/CLK1)
P6_1
P6_0(/TREO)
P5_7(/TRGIOB)
P5_6(/TRAO/TRGIOA)
P3_2(/INT1/INT2/TRAIO/TRGCLKB)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49 32 P8_4(/TRFO11)
50 31 P8_5(/TRFO12)
51 30 P8_6
52 29 P3_1(/TRBO)
53 28 P3_6(/INT1)
R8C/36A Group54 27 P2_0(/INT1/TRCIOB/TRDIOA0/TRDCLK)
55 26 P2_1(/TRCIOC/TRDIOC0)
56 25 P2_2(/TRCIOD/TRDIOB0)
57 PLQP0064KB-A (64P6Q-A) 24 P2_3(/TRDIOD0)
58 PLQP0064GA-A (64P6U-A) 23 P2_4(/TRDIOA1)
59 (Top view) 22 P2_5(/TRDIOB1)
60 21 P2_6(/TRDIOC1)
61 20 P2_7(/TRDIOD1)
62 19 P3_3/IVCMP3/INT3/SCS(/CTS2/RTS2/TRCCLK)
63 18 P3_4/IVREF3/SSI(/RXD2/SCL2/TXD2/SDA2/TRCIOC)
64 17 P3_5/SCL/SSCK(/CLK2/TRCIOD)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Notes:
1. Can be assigned to the pin in parentheses by a program.
2. P4_2 is an input-only pin.
3. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.3 Pin Assignment (Top View)
REJ03B0265-0110 Rev.1.10 Sep 28, 2009
Page 6 of 55

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R5F2136CANFP pdf, datenblatt
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/36A Group
2. Central Processing Unit (CPU)
2.1 Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-
bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5 Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2 Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5 Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009
Page 12 of 55

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