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Teilenummer | R5F21324ANSP |
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Beschreibung | MCU | |
Hersteller | Renesas | |
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Gesamt 30 Seiten R8C/32A Group
RENESAS MCU
REJ03B0229-0100
Rev.1.00
Sep 10, 2009
1. Overview
1.1 Features
The R8C/32A Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions
for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high
speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
The R8C/32A Group has data flash (1 KB × 4 blocks) with the background operation (BGO) function.
1.1.1 Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
REJ03B0229-0100 Rev.1.00 Sep 10, 2009
Page 1 of 53
R8C/32A Group
1. Overview
1.4 Pin Assignment
Figure 1.3 shows Pin Assignment (Top View). Table 1.4 outlines the Pin Name Information by Pin Number.
P4_2/VREF
MODE
RESET
P4_7/XOUT(/XCOUT)
VSS/AVSS
P4_6/XIN(/XCIN)
VCC/AVCC
P3_7/SDA/SSO/TRAO(/RXD2/SCL2/TXD2/SDA2)
P3_5/SCL/SSCK(/CLK2/TRCIOD)
P3_4/IVREF3/SSI(/RXD2/SCL2/TXD2/SDA2/TRCIOC)
1
2
3
4
5
6
7
8
9
10
20 P1_0/AN8/LVCMP1/KI0(/TRCIOD)
19 P1_1/AN9/LVCMP2/KI1(/TRCIOA/TRCTRG)
18 P1_2/AN10/LVREF/Kl2(/TRCIOB)
17 P1_3/AN11/LVCOUT1/Kl3/TRBO(/TRCIOC)
16 P1_4(/TXD0/TRCCLK)
15 P1_5(/INT1/RXD0/TRAIO)
14 P1_6/LVCOUT2/IVREF1(/CLK0)
13 P1_7/IVCMP1/INT1(/TRAIO)
12 P4_5/ADTRG/INT0(/RXD2/SCL2)
11 P3_3/IVCMP3/INT3/SCS(/CTS2/RTS2/TRCCLK)
Notes:
1. Can be assigned to the pin in parentheses by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.3 Pin Assignment (Top View)
REJ03B0229-0100 Rev.1.00 Sep 10, 2009
Page 6 of 53
6 Page R8C/32A Group
2. Central Processing Unit (CPU)
2.8.7 Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
REJ03B0229-0100 Rev.1.00 Sep 10, 2009
Page 12 of 53
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ R5F21324ANSP Schematic.PDF ] |
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