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RJF0611DPE Schematic ( PDF Datasheet ) - Renesas

Teilenummer RJF0611DPE
Beschreibung Silicon N Channel MOS FET
Hersteller Renesas
Logo Renesas Logo 




Gesamt 8 Seiten
RJF0611DPE Datasheet, Funktion
Target Specifications Datasheet
RJF0611DPE
Silicon N Channel MOS FET Series
Power Switching
R07DS0717EJ0100
Rev.1.00
Apr 17, 2012
Description
This FET has the over temperature shut-down capability sensing to the junction temperature. This FET has the built-in
over temperature shut-down circuit in the gate area. And this circuit operation to shut-down the gate voltage in case of
high junction temperature like applying over power consumption, over current etc..
Features
Logic level operation (4 V Gate drive).
Built-in the over temperature shut-down circuit.
High endurance capability against to the short circuit.
Latch type shut down operation (need 0 voltage recovery).
Built-in the current limitation circuit.
Power supply voltage applies 12 V and 24 V.
For Industrial applications
Outline
RENESAS Package code: PRSS0004AE-B
(Package name: LDPAK (S)-(1) )
4
123
G
Gate Resistor
Temperature
Sensing
Circuit
Latch
Circuit
Current
Limitation
Circuit
Gate
Shut-down
Circuit
D
1. Gate
2. Drain
3. Source
4. Drain
S
Absolute Maximum Ratings
Item
Symbol
Drain to source voltage
Gate to source voltage
Gate to source voltage
Drain current
Body-drain diode reverse drain current
Avalanche current
Avalanche energy
Channel dissipation
VDSS
VGSS
VGSS
ID Note3
IDR
IAP Note 2
EAR Note 2
Pch Note 1
Channel temperature
Tch
Storage temperature
Tstg
Notes: 1. Value at Tc = 25C
2. Tch = 25C, Rg 50
3. It provides by the current limitation lower bound value.
Ratings
60
16
–2.5
30
30
6.7
192
50
150
–55 to +150
(Ta = 25°C)
Unit
V
V
V
A
A
A
mJ
W
C
C
R07DS0717EJ0100 Rev.1.00
Apr 17, 2012
Page 1 of 7






RJF0611DPE Datasheet, Funktion
RJF0611DPE
Switching Time Test Circuit
Vin Monitor
D.U.T.
Vout
Monitor
RL
Vin
10 V
50 Ω
VDD
= 30 V
Target Specifications
Waveform
Vin
Vout
10%
10%
td(on)
90%
tr
90%
90%
td(off)
10%
tf
Vin
10 V
Avalanche Test Circuit
VDS
Monitor
Rg
L
IAP
Monitor
D. U. T
VDD
50 Ω
Avalanche Waveform
EAR = 1 L IAP2
2
V(BR)DSS
V(BR)DSS VDD
V(BR)DSS
IAP
ID VDS
VDD
0
R07DS0717EJ0100 Rev.1.00
Apr 17, 2012
Page 6 of 7

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