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R5F364AENFB Schematic ( PDF Datasheet ) - Renesas

Teilenummer R5F364AENFB
Beschreibung MCU
Hersteller Renesas
Logo Renesas Logo 




Gesamt 30 Seiten
R5F364AENFB Datasheet, Funktion
Datasheet
M16C/64A Group
RENESAS MCU
R01DS0032EJ0200
Rev.2.00
Feb 07, 2011
1. Overview
1.1 Features
The M16C/64A Group microcomputer (MCU) incorporates the M16C/60 Series CPU core and flash
memory, employing sophisticated instructions for a high level of efficiency. This MCU has 1 MB of address
space (expandable to 4 MB), and it is capable of executing instructions at high speed. In addition, the
CPU core boasts a multiplier for high-speed operation processing.
This MCU consumes low power, and supports operating modes that allow additional power control. The
MCU also uses an anti-noise configuration to reduce emissions of electromagnetic noise and is designed
to withstand electromagnetic interference (EMI). By integrating many of the peripheral functions, including
the multifunction timer and serial interface, the number of system components has been reduced.
1.1.1 Applications
This MCU can be used in audio components, cameras, televisions, household appliances, office
equipment, communication devices, mobile devices, industrial equipment, and other applications.
R01DS0032EJ0200 Rev.2.00
Feb 07, 2011
Page 1 of 88






R5F364AENFB Datasheet, Funktion
M16C/64A Group
1.4 Block Diagram
Figure 1.3 shows block diagram.
1. Overview
8
Port P0
8
Port P1
88
Port P2 Port P3
VCC2 ports
8
Port P4
8
Port P5
Internal peripheral functions
UART or
Timer (16 bit)
clock synchronous serial I/O
(6 channels)
Outputs (timer A): 5
Inputs (timer B): 6
Clock synchronous serial I/O
(8 bit x 2 channels)
Three-phase motor control
circuit
Multi-master I2C-bus interface
(1 channel)
Real-time clock
PWM function (8 bit x 2)
CEC function
Remote control signal
receiver (2 circuits)
System clock generator
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator (125 kHz)
DMAC (4 channels)
CRC calculator
(CRC-CCITT or CRC-16)
Voltage detector
Power-on reset
Watchdog timer
(15 bit)
On-chip debugger
A/D converter
(10-bit resolution x 26
channels)
D/A converter
(8-bit resolution x 2
circuits)
M16C/60 Series CPU core
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
Memory
ROM (1)
RAM (2)
Multiplier
Port P10
Port P9
VCC1 ports
Port P8
Port P7
8 88
8
Port P6
8
Notes:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Figure 1.3 Block Diagram for the 100-Pin Package
R01DS0032EJ0200 Rev.2.00
Feb 07, 2011
Page 6 of 88

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R5F364AENFB pdf, datenblatt
M16C/64A Group
1. Overview
Table 1.7 Pin Functions for the 100-Pin Package (2/3)
Signal Name
Pin Name
I/O
Power
Supply
Description
Main clock input
Main clock output
XIN
XOUT
I VCC1 I/O for the main clock oscillator. Connect a ceramic resonator
or crystal between pins XIN and XOUT. (1) Input an external
O VCC1 clock to XIN pin and leave XOUT pin open.
Sub clock input
Sub clock output
XCIN
XCOUT
I VCC1 I/O for a sub clock oscillator. Connect a crystal between XCIN
pin and XCOUT pin. (1) Input an external clock to XCIN pin and
O VCC1 leave XCOUT pin open.
BCLK output
BCLK
O VCC2 Outputs the BCLK signal.
Clock output
INT interrupt input
NMI interrupt input
CLKOUT
INT0 to INT2
INT3 to INT7
NMI
O VCC2 Outputs a clock with the same frequency as fC, f1, f8, or f32.
I VCC1
Input for the INT interrupt.
I VCC2
I VCC1 Input for the NMI interrupt.
Key input interrupt
input
KI0 to KI3
I VCC1 Input for the key input interrupt.
Timer A
TA0OUT to
TA4OUT
I/O
VCC1
I/O for timers A0 to A4 (TA0OUT is N-channel open drain
output).
TA0IN to TA4IN I VCC1 Input for timers A0 to A4.
ZP I VCC1 Input for Z-phase.
Timer B
Three-phase motor
control timer
TB0IN to TB5IN
U, U, V, V, W, W
SD
IDU, IDV, IDW
I
O
I
I
VCC1 Input for timers B0 to B5.
VCC1 Output for the three-phase motor control timer.
VCC1 Forced cutoff input.
VCC2 Input for the position data.
Real-time clock output RTCOUT
O VCC1 Output for the real-time clock.
PWM output
PWM0, PWM1
O
VCC1,
VCC2
PWM output.
Remote control signal
receiver input
PMC0, PMC1
I VCC1 Input for the remote control signal receiver.
CTS0 to CTS2,
CTS5
I
VCC1
Input pins to control data transmission.
CTS6, CTS7 I VCC2
RTS0 to RTS2,
RTS5
O
VCC1
Output pins to control data reception.
RTS6, RTS7 O VCC2
Serial interface
UART0 to UART2,
UART5 to UART7
CLK0 to CLK2,
CLK5
I/O
VCC1
Transmit/receive clock I/O.
CLK6, CLK7 I/O VCC2
RXD0 to RXD2,
RXD5
RXD6, RXD7
I
I
VCC1
Serial data input.
VCC2
TXD0 to TXD2,
TXD5
O
VCC1
Serial data output. (2)
TXD6, TXD7 O VCC2
CLKS1
O VCC1 Output for the transmit/receive clock multiple-pin output function.
Notes:
1. Contact the manufacturer of crystal/ceramic resonator regarding the oscillation characteristics.
2. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 5 to 7), SDAi, and SCLi can be
selected as CMOS output pins or N-channel open drain output pins.
R01DS0032EJ0200 Rev.2.00
Feb 07, 2011
Page 12 of 88

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