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87C52 Schematic ( PDF Datasheet ) - Intel

Teilenummer 87C52
Beschreibung CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Hersteller Intel
Logo Intel Logo 




Gesamt 23 Seiten
87C52 Datasheet, Funktion
8XC52 54 58
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Commercial Express
87C52 80C52 80C32 87C54 80C54 87C58 80C58
See Table 1 for Proliferation Options
Y High Performance CHMOS EPROM
ROM CPU
Y 12 24 33 MHz Operations
Y Three 16-Bit Timer Counters
Y Programmable Clock Out
Y Up Down Timer Counter
Y Three Level Program Lock System
Y 8K 16K 32K On-Chip Program Memory
Y 256 Bytes of On-Chip Data RAM
Y Improved Quick Pulse Programming
Algorithm
Y Boolean Processor
Y 32 Programmable I O Lines
Y 6 Interrupt Sources
Y Programmable Serial Channel with
Framing Error Detection
Automatic Address Recognition
Y TTL and CMOS Compatible Logic
Levels
Y 64K External Program Memory Space
Y 64K External Data Memory Space
Y MCS 51 Microcontroller Compatible
Instruction Set
Y Power Saving Idle and Power Down
Modes
Y ONCE (On-Circuit Emulation) Mode
Y Four-Level Interrupt Priority
Y Extended Temperature Range
(b40 C to a85 C)
MEMORY ORGANIZATION
ROM
Device
EPROM
Version
ROMless
Version
ROM EPROM
Bytes
80C52
87C52
80C32
8K
80C54
87C54
80C32
16K
80C58
87C58
80C32
32K
These devices can address up to 64 Kbytes of external program data memory
RAM
Bytes
256
256
256
The Intel 8XC52 8XC54 8XC58 is a single-chip control-oriented microcontroller which is fabricated on Intel’s
reliable CHMOS III-E technology Being a member of the MCS 51 family of controllers the 8XC52 8XC54
8XC58 uses the same powerful instruction set has the same architecture and is pin-for-pin compatible with
the existing MCS 51 family of products The 8XC52 8XC54 8XC58 is an enhanced version of the
87C51 80C51BH 80C31BH The added features make it an even more powerful microcontroller for applica-
tions that require clock output and up down counting capabilities such as motor control It also has a more
versatile serial channel that facilitates multi-processor communications
Throughout this document 8XC5X will refer to the 8XC52 80C32 8XC54 and 8XC58 unless information
applies to a specific device
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
October 1995
Order Number 272336-003






87C52 Datasheet, Funktion
8XC52 54 58
Mode
Idle
Idle
Power Down
Power Down
Table 2 Status of the External Pins during Idle and Power Down
Program
Memory
ALE
PSEN
PORT0
PORT1
PORT2
Internal
1
1
Data
Data
Data
External
1
1
Float
Data
Address
Internal
0
0
Data
Data
Data
External
0
0
Float
Data
Data
PORT3
Data
Data
Data
Data
POWER DOWN MODE
To save even more power a Power Down mode can
be invoked by software In this mode the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down mode is terminated
On the 8XC5X either a hardware reset or an external
interrupt can cause an exit from Power Down Reset
redefines all the SFRs but does not change the on-
chip RAM An external interrupt allows both the
SFRs and on-chip RAM to retain their values
To properly terminate Power Down the reset or ex-
ternal interrupt should not be executed before VCC is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms)
With an external interrupt INT0 and INT1 must be
enabled and configured as level-sensitive Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit Once the interrupt is
serviced the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down
DESIGN CONSIDERATION
 The window on the D87C5X must be covered by
an opaque label Otherwise the DC and AC char-
acteristics may not be met and the device may
be functionally impaired
 When the idle mode is terminated by a hardware
reset the device normally resumes program exe-
cution from where it left off up to two machine
cycles before the internal reset algorithm takes
control On-chip hardware inhibits access to inter-
nal RAM in this event but access to the port pins
is not inhibited To eliminate the possibility of an
unexpected write when Idle is terminated by re-
set the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory
ONCE MODE
The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates
testing and debugging of systems using the 8XC5X
without the 8XC5X having to be removed from the
circuit The ONCE Mode is invoked by
1) Pull ALE low while the device is in reset and
PSEN is high
2) Hold ALE low as RST is deactivated
While the device is in ONCE Mode the Port 0 pins
float and the other port pins and ALE and PSEN are
weakly pulled high The oscillator circuit remains ac-
tive While the 8XC5X is in this mode an emulator or
test CPU can be used to drive the circuit Normal
operation is restored when a normal reset is applied
NOTE
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I (Order No 270645) and Application Note AP-252 (Embedded Applications Handbook Order No
270648) ‘‘Designing with the 80C51BH ’’
6

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87C52 pdf, datenblatt
8XC52 54 58
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters The first char-
acter is always a ‘T’ (stands for time) The other
characters depending on their positions stand for
the name of a signal or the logical status of that
signal The following is a list of all the characters and
what they stand for
A Address
C Clock
D Input Data
H Logic level HIGH
I Instruction (program memory contents)
L Logic level LOW or ALE
P PSEN
Q Output Data
R RD signal
T Time
V Valid
W WR signal
X No longer a valid logic level
Z Float
For example
TAVLL e Time from Address Valid to ALE Low
TLLPL e Time from ALE Low to PSEN Low
AC CHARACTERISTICS (Over Operating Conditions Load Capacitance for Port 0 ALE PROG and
PSEN e 100 pF Load Capacitance for All Other Outputs e 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
All parameter values apply to all devices unless otherwise indicated In this table 8XC5X refers to 8XC5X
8XC5X-1 and 8XC5X-2
Oscillator
Symbol
Parameter
12 MHz 24 MHz 33 MHz
Variable
Units
Min Max Min Max Min Max
Min
Max
1 TCLCL Oscillator Frequency
8XC5X
8XC5X-1
8XC5X-2
8XC5X-24
8XC5X-33
3 5 12 MHz
3 5 16 MHz
0 5 12 MHz
3 5 24 MHz
3 5 33 MHz
TLHLL ALE Pulse Width
127
43
21 2 TCLCL b 40
ns
TAVLL Address Valid to
ALE Low
8XC5X
43
TCLCL b 40
8XC5X-24
12 TCLCL b 30
8XC5X-33
5 TCLCL b 25
ns
ns
ns
TLLAX Address Hold After
ALE Low
8XC5X -24 53 12
TCLCL b 30
8XC5X-33
5 TCLCL b 25
ns
ns
TLLIV
ALE Low to Valid
Instruction In
8XC5X
8XC5X-24
8XC5X-33
234
91
56
4 TCLCL b 100
4 TCLCL b 75
4 TCLCL b 65
ns
ns
ns
12

12 Page





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