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P4C164LL Schematic ( PDF Datasheet ) - PYRAMID

Teilenummer P4C164LL
Beschreibung STATIC CMOS RAM
Hersteller PYRAMID
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Gesamt 10 Seiten
P4C164LL Datasheet, Funktion
FEATURES
VCC Current (Commercial/Industrial)
— Operating: 55 mA
— CMOS Standby: 3 µA
Access Times
—80/100 (Commercial or Industrial)
—90/120 (Military)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE1, CE2 and OE
Inputs
P4C164LL
VERY LOW POWER 8Kx8
STATIC CMOS RAM
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—28-Pin 300 and 600 mil DIP
—28-Pin 330 mil SOP
DESCRIPTION
The P4C164LL is a 64K density low power CMOS static
RAM organized as 8Kx8. The CMOS memory requires
no clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply.
Access times of 80 and 100 ns are available for commercial
and industrial temperatures; access times of 90 and 100
ns are available for military temperature. CMOS is utilized
to reduce power consumption to a low level.
The P4C164LL device provides asynchronous operation
with matching access and cycle times.
Memory locations are specified on address pins A0 to A12.
Reading is accomplished by device selection (CE1 LOW,
CE2 HIGH ) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory loca-
tion is presented on the data input/output pins. The input/
output pins stay in the HIGH Z state when either CE1 or
OE is HIGH or WE or CE2 is LOW.
Package options for the P4C164LL include 28-pin 300 and
600 mil DIP and 28-pin 330 mil SOP packages.
Functional Block Diagram
Pin ConfigurationS
Document # SRAM116 REV 04
DIP (P5, P6, C5-1), SOP (S5)
TOP VIEW
Revised June 2014






P4C164LL Datasheet, Funktion
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
Timing Waveform of Write Cycle No. 2 (CE Controlled)(6)
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
TRUTH TABLE
Mode
Standby
CE1 CE2 OE WE I/O
H X X X High Z
Standby
X L X X High Z
DOUT Disabled L H H H High Z
Read
L H L H DOUT
Write
L H X L High Z
Power
Standby
Standby
Active
Active
Active
Figure 1. Output Load
* including scope and test fixture.
Figure 2. Thevenin Equivalent
Note:
Because of the ultra-high speed of the P4C164LL, care must be taken
when testing this device; an inadequate setup can cause a normal function-
ing part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at
the comparator input, and a 589Ω resistor must be used in series with
DOUT to match 639Ω (Thevenin Resistance).
Document # SRAM116 REV 04
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