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P4C1281 Schematic ( PDF Datasheet ) - PYRAMID

Teilenummer P4C1281
Beschreibung STATIC CMOS RAM
Hersteller PYRAMID
Logo PYRAMID Logo 




Gesamt 11 Seiten
P4C1281 Datasheet, Funktion
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 12/15/20/25 ns (Commercial)
– 15/20/25/35 ns (Industrial)
– 20/25/35/45 ns (Military)
Low Power Operation
5V ± 10% Power Supply
P4C1281/P4C1282
ULTRA HIGH SPEED 64K X 4
cmos STATIC RAMS
Separate Inputs and Outputs
– P4C1281 Input Data at Outputs during Write
– P4C1282 Outputs in High Z during Write
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350 x 550 mil LCC
DESCRIPTION
The P4C1281 and P4C1282 are 262,144-bit (64Kx4) ultra
high-speed static RAMs similar to the P4C1258, but with
separate data I/O pins. The P4C1281 features a transpar-
ent write operation; the outputs of the P4C1282 are in high
impedance during the write cycle. The RAMs operate from
a single 5V ± 10% tolerance power supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption.
The P4C1281 and P4C1282 are available in 28-pin 300
mil DIP and SOJ, and a 28-pin 350x550 mil LCC providing
excellent board level densities.
Functional Block Diagram
Pin ConfigurationS
Document # SRAM136 REV OR
DIP (P5, C5, D5-2), SOJ (J5)
LCC (L5)
Revised July 2009






P4C1281 Datasheet, Funktion
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
TRUTH TABLE P4C1281 (P4C1282)
Mode
CE WE I/O
Standby
H X High Z
Read
Write
L H DOUT
L L DIN (High Z)
Power
Standby
Active
Active
Figure 1. Output Load
* including scope and test fixture.
Figure 2. Thevenin Equivalent
Note:
Because of the ultra-high speed of the P4C1281 and P4C1282, care
must be taken when testing this device; an inadequate setup can cause
a normal functioning part to be rejected as faulty. Long high-inductance
leads that cause supply bounce must be avoided by bringing the VCC
and ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground. To avoid
signal reflections, proper termination must be used; for example, a 50Ω test
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with DOUT to match 166Ω (Thevenin Resistance).
Document # SRAM136 REV OR
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