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PDF P4C1257L Data sheet ( Hoja de datos )
| Número de pieza | P4C1257L | |
| Descripción | STATIC CMOS RAM | |
| Fabricantes | PYRAMID | |
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FEATURES
Full CMOS
High Speed (Equal Access and Cycle Times)
– 12/15/20/25 ns (Commercial)
– 12/15/20/25 ns (Industrial)
– 25/35/45/55/70 ns (Military)
Single 5V±10% Power Supply
Data Retention with 2.0V Power Supply
(P4C1257L)
P4C1257/P4C1257L
ULTRA HIGH SPEED 256K x 1
STATIC CMOS RAMS
Separate Data I/O
Three-State Output
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP, SOJ
– 28-Pin 350x550 mil LCC
– 28-Pin Flatpack
DESCRIPTION
The P4C1257/P4C1257L are 256Kx1-bit ultra high-speed
static RAMs. The CMOS memories require no clocks or
refreshing and have equal access and cycle times. The
RAMs operate from a single 5V ± 10% tolerance power
supply. Data integrity is maintained for supply voltages
down to 2.0V, typically drawing 10µA.
Access times as fast as 12 nanoseconds are available,
greatly enhancing system speeds.
The P4C1257/P4C1257L are available in 24-pin 300 mil
DIP and SOJ, 28-pin LCC and Flatpack packages, provid-
ing excellent board level densities.
Functional Block Diagram
Pin ConfigurationS
Document # SRAM137 REV 01
DIP (P4, C4)
SOJ (J4)
LCC (L5)
Revised June 2013
1 page  
P4C1257/P4C1257L - ULTRA HIGH SPEED 256K X 1 STATIC CMOS RAMS
TIMING WAVEFORM OF WRITE Cycle No. 1 (WE Controlled)(10,11)
Timing Waveform of Write Cycle No. 2 (CE Controlled)(10)
Notes:
1. Stresses greater than those listed under Maximum Ratings may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to Maximum rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM137 REV 01
Page 5
5 Page 
P4C1257/P4C1257L - ULTRA HIGH SPEED 256K X 1 STATIC CMOS RAMS
REVISIONS
DOCUMENT NUMBER SRAM137
DOCUMENT TITLE
P4C1257/P4C1257L - ULTRA HIGH SPEED 256K X 1 STATIC CMOS RAMS
REV
OR
01
ISSUE DATE
Aug-2009
Jun-2013
ORIGINATOR DESCRIPTION OF CHANGE
JDB New Data Sheet
JDB
Document # SRAM137 REV 01
Page 11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet P4C1257L.PDF ] | |
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