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DK2051 Schematic ( PDF Datasheet ) - RF Micro Devices

Teilenummer DK2051
Beschreibung HIGH PERFORMANCE WIDEBAND RF PLL/VCO
Hersteller RF Micro Devices
Logo RF Micro Devices Logo 




Gesamt 30 Seiten
DK2051 Datasheet, Funktion
RF2051RF2051
HIGH PERFORMANCE WIDEBAND RF PLL/VCO WITH
INTEGRATED RF MIXERS
Package: QFN, 32-Pin, 5mmx5mm
Features
30MHz to 2.5GHz Frequency
Range
Fractional-N Synthesizer
Very Fine Frequency Resolution
1.5Hz for 26MHz Reference
Low Phase Noise VCO
On-Chip Crystal-Sustaining
Circuit With Programmable
Loading Capacitors
Two High-Linearity RF Mixers
Integrated LO Buffers
Mixer Input IP3 +18dBm
Mixer Bias Adjustable for Low
Power Operation
Full Duplex Mode
2.7V to 3.6V Power Supply
Low Current Consumption
55mA to 75mA at 3V
3-Wire Serial Interface
Applications
CATV Head-Ends
Digital TV Up/Down Converters
Digital TV Repeaters
Multi-Dwelling Units
Cellular Repeaters
Frequency Band Shifters
UHF/VHF Radios
Diversity Receivers
Software Defined Radios
Satellite Communications
Super-Heterodyne Radios
VCO
LO
divider
Synth
Frac-N
sequence
generator
Charge
pump
N divider
Phase /
freq
detector
Mux
LO
divider
Ref
divider
Functional Block Diagram
Product Description
The RF2051 is a low power, high performance, wideband RF frequency conversion
chip with integrated local oscillator (LO) generation and a pair of RF mixers. The RF
synthesizer includes an integrated fractional-N phase locked loop with voltage con-
trolled oscillators (VCOs) and dividers to produce a low-phase noise LO signal with a
very fine frequency resolution. The buffered LO output drives the built-in RF mixers
which convert the signal into the required frequency band. The mixer bias current
can be programmed dependent on the required performance and available supply
current. The LO generation blocks have been designed to continuously cover the
frequency range from 300MHz to 2400MHz. The RF mixers are very broad band
and operate from 30MHz to 2500MHz at the input and output, enabling both up
and down conversion. An external crystal of between 10MHz and 52MHz or an
external reference source of between 10MHz and 104MHz can be used with the
RF2051 to accommodate a variety of reference frequency options.
All on-chip registers are controlled through a simple three-wire serial interface. The
RF2051 is designed for 2.7V to 3.6V operation for compatibility with portable, bat-
tery powered devices. It is available in a plastic 32-pin, 5mmx5mm QFN package.
Optimum Technology Matching® Applied
GaAs HBT
GaAs MESFET
InGaP HBT
SiGe BiCMOS
Si BiCMOS
SiGe HBT
GaAs pHEMT
Si CMOS
Si BJT
GaN HEMT
RF MEMS
DS140110
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trade-
mark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2006, RF Micro Devices, Inc.
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
1 of 39






DK2051 Datasheet, Funktion
RF2051
Typical Performance Characteristics: Synthesizer and VCO - VDD=3V, TA=25°C, as measured on RF2051 evaluation board,
for application schematic see page 36. Phase Detector Frequency=26MHz, Loop Bandwidth=60kHz.
VCO1 With Active Loop Filter
VCO1 With Passive Loop Filter
-60 -60
2000MHz
2000MHz
1000MHz
1000MHz
-80
500MHz
-80
500MHz
-100
-100
-120
-120
-140
-140
-160
1
-60
-80
10 100 1000
Offset Frequency (kHz)
VCO2 With Active Loop Filter
10000
1600MHz
800MHz
400MHz
-160
1
-60
-80
10 100 1000
Offset Frequency (kHz)
VCO2 With Passive Loop Filter
10000
1600MHz
800MHz
400MHz
-100
-100
-120
-120
-140
-140
-160
1
-60
-80
10 100 1000
Offset Frequency (kHz)
VCO3 With Active Loop Filter
10000
1200MHz
600MHz
300MHz
-160
1
-60
-80
10 100 1000
Offset Frequency (kHz)
VCO3 With Passive Loop Filter
10000
1200MHz
600MHz
300MHz
-100
-100
-120
-120
-140
-140
-160
1
10 100 1000
Offset Frequency (kHz)
10000
-160
1
10 100 1000
Offset Frequency (kHz)
10000
6 of 39
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS140110

6 Page









DK2051 pdf, datenblatt
RF2051
Fractional-N PLL
The IC contains a charge-pump based fractional-N phase locked loop (PLL) for controlling the three VCOs. The PLL includes
automatic calibration systems to counteract the effects of process and environmental variations, ensuring repeatable lock-
time and noise performance. The PLL is intended to use a reference frequency signal of 10MHz to 104MHz. A reference
divider (divide by 1 to divide by 7) is supplied and should be programmed to limit the frequency at the phase detector to a max-
imum of 52MHz. The reference divider bypass is controlled by bit CLK DIV_BYP, set low to enable the reference divider and set
high for divider bypass (divide by 1). The remaining three bits CLK DIV<15:13> set the reference divider value, divide by 2
(010) to 7 (111) when the reference divider is enabled.
Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the
label PLL2. For the RF2051 these banks are used to program mixer 1 and mixer 2 respectively, and are selected automatically
as the mixer is selected (using the MODE pin).
The PLL will lock the VCO to the frequency FVCO according to:
FVCO =NEFF*FOSC/R
where NEFF is the programmed fractional N divider value, FOSC is the reference input frequency, and R is the programmed R
divider value (1 to 7).
The N divider is a fractional divider, containing a dual-modulus prescaler and a digitally spur-compensated fractional sequence
generator to allow fine frequency steps. The N divider is programmed using the N and NUM bits as follows:
First determine the desired, effective N divider value, NEFF:
NEFF = FVCO*R/FOSC
N(9:0) should be set to the integer part of NEFF. NUM should be set to the fractional part of NEFF multiplied by 224=16777216.
Example: VCO1 operating at 2220MHz, 23.92MHz reference frequency, the desired effective divider value is:
NEFF=FVCO *R / FOSC=2220 *1 / 23.92=92.80936454849.
The N value is set to 92, equal to the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied
by 224:
NUM=0.80936454849 * 224=13,578,884.
Converting N and NUM into binary results in the following:
N=0 0101 1100
NUM=1100 1111 0011 0010 1000 0100
So the registers would be programmed:
P1_N (or P2_N)=0 0101 1100
P1_NUM_MSB (or P2_NUM_MSB)=1100 1111 0011 0010
P1_NUM_LSB (or P2_NUM_LSB)=1000 0100
The maximum NEFF is 511, and the minimum NEFF is 15, when in fractional mode. The minimum step size is FOSC/R*224. Thus
for a 23.92MHz reference, the frequency step size would be 1.4Hz. The minimum reference frequency that could be used to
program a frequency of 2400MHz (using VCO1) is 2400/511, 4.697MHz (approx).
12 of 39
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS140110

12 Page





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