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RF2054 Schematic ( PDF Datasheet ) - RF Micro Devices

Teilenummer RF2054
Beschreibung LOW POWER PLL AND VCO
Hersteller RF Micro Devices
Logo RF Micro Devices Logo 




Gesamt 30 Seiten
RF2054 Datasheet, Funktion
RF2054Low
Power PLL and
VCO with Inte-
grated Mixers
RF2054
LOW POWER PLL AND VCO WITH INTEGRATED
MIXERS
Package: QFN, 32-Pin, 5mm x 5mm
Features
Fractional-N Synthesizer
Very Fine Frequency Resolution
1.5Hz for 26MHz Reference
LO Frequency Range 940MHz to
1000MHz
Low Phase Noise VCO
Integrated LO Buffers
Two Wideband RF Mixers
Mixer Frequency Range 30MHz
to 2500MHz
Mixer Input IP3 +12dBm
Mixer Bias Adjustable for Low
Power Operation
2.1V to 2.3V Power Supply
Low Current Consumption
45mA typ. at 2.2V
3-Wire Serial Interface
Applications
Band Shifters
Super-Heterodyne Radios
Diversity Receivers
Wireless Telemetry
VCO
LO
divider
Synth
Frac-N
sequence
generator
Charge
pump
N
divider
Phase /
freq
detector
Sw
LO
divider
Ref
divider
Functional Block Diagram
Product Description
The RF2054 is a low power, high performance, frequency conversion chip with inte-
grated local oscillator (LO) and a pair of RF mixers. The synthesizer includes an inte-
grated fractional-N phase locked loop that can control the VCO to produce a low
phase noise and low spurious LO signal with very fine frequency resolution. The
VCO output can then be divided by one, two, or four in the LO divider, the output of
which drives the mixer, which converts the signal into the required frequency band.
The LO generation block has been optimized to operate with the VCO covering the
frequency range from 940MHz to 1000MHz, set by the value of the external induc-
tor used. The mixers are broadband and can operate from 30MHz to 2500MHz at
the input and output, enabling both up and down conversion. An external reference
source of between 10MHz and 26MHz can be used with the RF2054.
All on-chip registers are controlled through a simple three-wire serial interface. The
RF2054 has been characterized for 2.2V operation and low power consumption. It
is available in a plastic 32-pin, 5mm x 5mm QFN package.
DS120320
Optimum Technology Matching® Applied
GaAs HBT
GaAs MESFET
InGaP HBT
SiGe BiCMOS
Si BiCMOS
SiGe HBT
GaAs pHEMT
Si CMOS
Si BJT
GaN HEMT
BiFET HBT
LDMOS
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trade-
mark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2012, RF Micro Devices, Inc.
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
1 of 39






RF2054 Datasheet, Funktion
RF2054
Typical Performance Characteristics: PLL and VCO
VDD = +2.2V, TA = +25°C unless stated, as measured on RF2054 evaluation board.
See schematic page 36.
Synthesizer Phase Noise versus Frequency
21MHz Reference and +2.2V Supply
-60.0
Synthesizer Phase Noise versus Temperature
LO = 960MHz, 21MHz Reference and +2.2V Supply
-60.0
-80.0
-80.0
-100.0
-120.0
-140.0
-160.0
1.0
940MHz
960MHz
980MHz
1000MHz
10.0
100.0
1000.0
Offset Frequency (kHz)
10000.0
-100.0
-120.0
-140.0
-160.0
1.0
-20ƒC
0ƒC
+25ƒC
+50ƒC
+75ƒC
10.0
100.0
1000.0
Offset Frequency (kHz)
10000.0
VCO Phase Noise versus Frequency
+2.2V Supply
-20.0
-40.0
-60.0
-80.0
940MHz
960MHz
980MHz
1000MHz
-100.0
-120.0
-140.0
-160.0
1.0
10.0
100.0
1000.0
Offset Frequency (kHz)
10000.0
VCO Phase Noise versus Temperature
VCO Frequency 960MHz, +2.2V Supply
-20.0
-40.0
-60.0
-80.0
-20ƒC
0ƒC
+25ƒC
+50ƒC
+75ƒC
-100.0
-120.0
-140.0
-160.0
1.0
10.0
100.0
1000.0
Offset Frequency (kHz)
10000.0
VCO Coarse Tuning versus Frequency
3.3nH VCO Inductors and +2.2V Supply
125.0
100.0
75.0
-20ƒC
50.0
0ƒC
+25ƒC
+50ƒC
25.0
+75ƒC
0.0
800
900
1000
1100
VCO Frequency (MHz)
1200
1300
VCO Frequency versus Tuning Voltage and Temperature
For the Same Coarse Tune Setting, +2.2V Supply
970
965
960
955
950
945
940
0.0
-20ƒC
0ƒC
+25ƒC
+50ƒC
+75ƒC
0.5 1.0 1.5
Tuning Voltage (Volts)
2.0
6 of 39
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS120320

6 Page









RF2054 pdf, datenblatt
RF2054
Fractional-N PLL
The RF2054 contains a charge-pump based fractional-N phase locked loop (PLL) for controlling the VCO. The PLL includes
automatic calibration systems to counteract the effects of process and environmental variations, ensuring repeatable lock
time and noise performance. The PLL is intended to use a reference frequency signal of 10MHz to 26MHz. The reference path
features a divider, but typically for best phase noise this is bypassed. The reference divider bypass is controlled by bit CLK
DIV_BYP, set low to enable the reference divider and set high for divider bypass (divide by 1). The remaining three bits CLK DIV
<15:13> set the reference divider value, divide by 2 (010) to 7 (111) when the reference divider is enabled.
Two PLL programming banks are provided, the first bank is preceded by the label PLL1, and the second bank is preceded by
the label PLL2. For the RF2054, these banks are used to program mixer 1 and mixer 2 respectively, and are selected automat-
ically as the mixer is selected (using the MODE pin).
The PLL will lock the VCO to the frequency FVCO according to:
FVCO = NEFF*FOSC/R
where NEFF is the programmed fractional-N divider value, FOSC is the reference input frequency, and R is the programmed R
divider value (1 to 7).
The N divider is a fractional divider, containing a dual-modulus prescaler and a digitally spur-compensated fractional sequence
generator to allow fine frequency steps. The N divider is programmed using the N and NUM bits as follows:
First determine the desired, effective N divider value, NEFF:
NEFF = FVCO*R/FOSC
N(9:0) should be set to the integer part of NEFF. NUM should be set to the fractional part of NEFF multiplied by 224 = 16777216.
Example: VCO3 operating at 960MHz, 21MHz reference frequency, the desired effective divider value is:
NEFF = FVCO *R / FOSC = 960 *1 / 21 = 45.714285714285.
The N value is set to 45, equal to the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied
by 224:
NUM = 0.714285714285 * 224 = 11983726.
Converting N and NUM into binary results in the following:
N = 0001 0110 1
NUM = 1011 0110 1101 1011 0110 1110
So the registers would be programmed:
P1_N (or P2_N) = 0001 0110 1
P1_NUM_MSB (or P2_NUM_MSB) = 1011 0110 1101 1011
P1_NUM_LSB (or P2_NUM_LSB) = 0110 1110
The maximum NEFF is 511, and the minimum NEFF is 15, when in fractional mode.
12 of 39
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS120320

12 Page





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