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8T49N286 Schematic ( PDF Datasheet ) - Integrated Device Technology

Teilenummer 8T49N286
Beschreibung NG Octal Universal Frequency Translator
Hersteller Integrated Device Technology
Logo Integrated Device Technology Logo 




Gesamt 30 Seiten
8T49N286 Datasheet, Funktion
FemtoClock® NG Octal Universal
Frequency Translator
8T49N286
Datasheet
General Description
The 8T49N286 has two independent, fractional-feedback PLLs that
can be used as jitter attenuators and frequency translators. It is
equipped with six integer and two fractional output dividers, allowing
the generation of up to eight different output frequencies, ranging
from 8kHz to 1GHz. Four of these frequencies are completely
independent of each other and the inputs. The other four are related
frequencies. The eight outputs may select among LVPECL, LVDS,
HCSL or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency
translation application, including 1G, 10G, 40G and 100G
Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T
G.709 (2009) FEC rates. The device may also behave as a frequency
synthesizer.
The 8T49N286 accepts up to four differential or single-ended input
clocks and a crystal input. Each of the two internal PLLs can lock to
different input clocks which may be of independent frequencies. The
other two input clocks are intended for redundant backup of the
primary clocks and must be related in frequency to their primary.
The device supports hitless reference switching between input
clocks. The device monitors all input clocks for Loss of Signal (LOS),
and generates an alarm when an input clock failure is detected.
Automatic and manual hitless reference switching options are
supported. LOS behavior can be set to support gapped or un-gapped
clocks.
The 8T49N286 supports holdover for each PLL. The holdover has an
initial accuracy of ±50ppB from the point where the loss of all
applicable input reference(s) has been detected. It maintains a
historical average operating point for each PLL that may be returned
to in holdover at a limited phase slope.
The device places no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error.
Each PLL has a register-selectable loop bandwidth from 1.4Hz to
360Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I2C interface. It also supports
I2C master capability to allow the register configuration to be read
from an external EEPROM. The user may select whether the
programming interface uses I2C protocols or SPI protocols, however
in SPI mode, read from the external EEPROM is not supported.
Applications
OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
OTN de-mapping (Gapped Clock and DCO mode)
Gigabit and Terabit IP switches / routers including support of
Synchronous Ethernet
SyncE (G.8262) applications
Wireless base station baseband
Data communications
100G Ethernet
Features
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
<0.3ps RMS Typical Jitter (including spurs), 12kHz to 20MHz
Operating modes: locked to input signal, holdover and free-run
Initial holdover accuracy of ±50ppb
Accepts up to four LVPECL, LVDS, LVHSTL, HCSL or LVCMOS
input clocks
Accepts frequencies ranging from 8kHz up to 875MHz
Auto and manual input clock selection with hitless switching
Clock input monitoring, including support for gapped clocks
Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
Operates from a 10MHz to 40MHz fundamental-mode crystal
Generates 8 LVPECL / LVDS / HCSL or 16 LVCMOS output
clocks
Output frequencies ranging from 8kHz up to 1.0GHz (diff)
Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
Eight General Purpose I/O pins with optional support for status
and control
Eight Output Enable control inputs
Lock, Holdover and Loss-of-Signal status outputs
Open-drain Interrupt pin
Write-protect pin to prevent configuration registers being altered
Nine programmable loop bandwidth settings for each PLL from
1.4Hz to 360Hz.
Optional Fast Lock function
Programmable output phase delays in steps as small as 16ps
Register programmable through I2C / SPI or via external I2C
EEPROM
Bypass clock paths for system tests
Power supply modes:
VCC / VCCA / VCCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
-40°C to 85°C ambient operating temperature
Package: 72QFN, lead-free RoHs (6)
©2016 Integrated Device Technology, Inc.
1
Revision 7, October 27, 2016






8T49N286 Datasheet, Funktion
8T49N286 Datasheet
Table 2. Pin Characteristics, VCC = VCCOX = 3.3V±5% or 2.5V±5%
Symbol
Parameter
Test Conditions
CIN
RPULLUP
Input Capacitance; NOTE 1
Internal Pullup
Resistor
nRST, nWP,
SDATA / SDO,
SCLK / SCLK
nINT
GPIO[7:0]
RPULLDOWN
Internal Pulldown Resistor
LVCMOS
Q[0:1], Q[4:7]
VCCOX = 3.465V
LVCMOS Q[2:3]
LVCMOS
Q[0:1], Q[4:7]
VCCOX = 3.465V
VCCOX = 2.625V
Power
LVCMOS Q[2:3]
CPD
Dissipation
Capacitance
LVCMOS
Q[0:1], Q[4:7]
(per output pair) LVCMOS Q[2:3]
VCCOX = 2.625V
VCCOX = 1.89V
VCCOX = 1.89V
LVDS, HCSL or
LVPECL Q[0:1],
Q[4:7]
VCCOx = 3.465V or 2.625V
LVDS, HCSL or
LVPECL Q[2:3]
VCCOx = 3.465V or 2.625V
ROUT
Output
Impedance
GPIO[7:0]
LVCMOS
Q[7:0], nQ[7:0]
Output HIGH
Output LOW
NOTE: VCCOX denotes: VCCO0 through VCCO7.
NOTE 1: This specification does not apply to OSCI and OSCO pins.
Minimum
Typical
3.5
Maximum Units
pF
51 k
50 k
5.1 k
51 k
14.5 pF
18.5 pF
13 pF
17.5 pF
12.5 pF
17 pF
2 pF
4.5 pF
5.1 k
25
20
©2016 Integrated Device Technology, Inc.
6
Revision 7, October 27, 2016

6 Page









8T49N286 pdf, datenblatt
8T49N286 Datasheet
Device Start-up & Reset Behavior
The 8T49N286 has an internal power-up reset (POR) circuit and a
Master Reset input pin nRST. If either is asserted, the device will be
in the Reset State.
For highly programmable devices, it’s common practice to reset the
device immediately after the initial power-on sequence. IDT
recommends connecting the nRST input pin to a programmable logic
source for optimal functionality. It is recommended that a minimum
pulse width of 10ns be used to drive the nRST input pin.
While in the reset state (nRST input asserted or POR active), the
device will operate as follows:
• All registers will return to & be held in their default states as
indicated in the applicable register description.
• All internal state machines will be in their reset conditions.
• The serial interface will not respond to read or write cycles.
• The GPIO signals will be configured as OE[7:0] inputs.
• All clock outputs will be disabled.
• All interrupt status and Interrupt Enable bits will be cleared,
negating the nINT signal.
Upon the latter of the internal POR circuit expiring or the nRST input
negating, the device will exit reset and begin self-configuration.
The device will load an initial block of its internal registers using the
configuration stored in the internal One-Time Programmable (OTP)
memory. Once this step is complete, the 8T49N286 will check the
register settings to see if it should load the remainder of its
configuration from an external I2C EEPROM at a defined address or
continue loading from OTP. See the section on I2C Boot-up
Initialization Mode for details on how this is performed.
Once the full configuration has been loaded, the device will respond
to accesses on the serial port and will attempt to lock both PLLs to
the selected sources and begin operation. Once the PLLs are locked,
all the outputs derived from a given PLL will be synchronized and
output phase adjustments can then be applied if desired.
Serial Control Port Description
Serial Control Port Configuration Description
The device has a serial control port capable of responding as a slave
in an I2C or SPI compatible configuration, to allow access to any of
the internal registers for device programming or examination of
internal status. All registers are configured to have default values.
See the specifics for each register for details. Selection of I2C versus
SPI protocol will be done via an input pin.
The device has the additional capability of becoming a master on the
I2C bus only for the purpose of reading its initial register
configurations from a serial EEPROM on the I2C bus. Writing of the
configuration to the serial EEPROM must be performed by another
device on the same I2C bus or pre-programmed into the device prior
to assembly. This capability is unavailable if SPI protocols are
selected for the programming interface.
SPI Mode Operation
In a read operation (R/W bit is '1') data on SDO will be clocked out on
the falling edge of SCLK.
In a write operation (R/W bit is '0'), data on SDI will be clocked in on
the rising edge of SCLK.
Read (LSB first)
nCS
SCLK
SDI
SDO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R/W A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Hi-Z
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Figure 3. SPI Read Sequencing Diagram
©2016 Integrated Device Technology, Inc.
12
Revision 7, October 27, 2016

12 Page





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