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W9816G6CH Schematic ( PDF Datasheet ) - Winbond

Teilenummer W9816G6CH
Beschreibung 512K x 2 BANKS x 16 BITS SDRAM
Hersteller Winbond
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Gesamt 30 Seiten
W9816G6CH Datasheet, Funktion
W9816G6CH
512K × 2 BANKS × 16 BITS SDRAM
Table of Content-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. PART NUMBER INFORMATION................................................................................................ 3
4. PIN CONFIGURATION ............................................................................................................... 4
5. PIN DESCRIPTION..................................................................................................................... 5
6. BLOCK DIAGRAM ...................................................................................................................... 6
7. FUNCTIONAL DESCRIPTION ................................................................................................... 7
7.1 Power Up and Initialization ............................................................................................. 7
7.2 Programming Mode Register.......................................................................................... 7
7.3 Bank Activate Command ................................................................................................ 7
7.4 Read and Write Access Modes ...................................................................................... 7
7.5 Burst Read Command .................................................................................................... 8
7.6 Burst Write Command .................................................................................................... 8
7.7 Read Interrupted by a Read ........................................................................................... 8
7.8 Read Interrupted by a Write............................................................................................ 8
7.9 Write Interrupted by a Write............................................................................................ 8
7.10 Write Interrupted by a Read............................................................................................ 8
7.11 Burst Stop Command ..................................................................................................... 9
7.12 Addressing Sequence of Sequential Mode .................................................................... 9
7.13 Addressing Sequence of Interleave Mode ..................................................................... 9
7.14 Auto-precharge Command ........................................................................................... 10
7.15 Precharge Command.................................................................................................... 10
7.16 Self Refresh Command ................................................................................................ 10
7.17 Power Down Mode ....................................................................................................... 11
7.18 No Operation Command............................................................................................... 11
7.19 Deselect Command ...................................................................................................... 11
7.20 Clock Suspend Mode.................................................................................................... 11
8. TABLE OF OPERATING MODES ............................................................................................ 12
9. ABSOLUTE MAXIMUM RATINGS ........................................................................................... 13
10. RECOMMENDED DC OPERATING CONDITIONS................................................................. 13
11. CAPACITANCE......................................................................................................................... 13
12. DC CHARACTERISTICS.......................................................................................................... 14
Publication Release Date: June 10, 2005
- 1 - Revision A0






W9816G6CH Datasheet, Funktion
6. BLOCK DIAGRAM
W9816G6CH
CLK
CKE
CLOCK
BUFFER
CS
RAS
CAS
WE
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
A10
MODE
A0 REGISTER
A9
BA
ADDRESS
BUFFER
COLUMN DECODER
R
O
W CELL ARRAY
D
E
BANK #0
C
O
D
E
R
SENSE AMPLIFIER
DATA CONTROL
CIRCUIT
DQ
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
COLUMN DECODER
R
O
W
D CELL ARRAY
E
C
BANK #1
O
D
E
R
SENSE AMPLIFIER
Note: The cell array configuration is 2048 * 256 * 16
DQ0
DQ15
LDQM
UDQM
-6-

6 Page









W9816G6CH pdf, datenblatt
W9816G6CH
8. TABLE OF OPERATING MODES
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
TABLE 1 TRUTH TABLE (NOTE 1, 2)
COMMAND
DEVICE
STATE
CKEN-1 CKEN
DQM BA
A10
A9-
0
CS
RAS CAS
WE
Bank Active
Idle H X X V V V L L H H
Bank Precharge Any H X X V L X L L H L
Precharge All
Any H X X X H X L L H L
Write
Active (3) H
X X VL V L H L L
Write with
Autoprecharge
Active (3) H
X X VH V L H L L
Read
Active (3) H
X X VL V L H L H
Read with
Autoprecharge
Active (3) H
X X VH V L H L H
Mode Register Set Idle H X X V V V L L L L
No-Operation
Any H X X X X X L H H H
Burst Stop
Active (4) H
X X XX X L H H L
Device Deselect Any H X X X X X H X X X
Auto-Refresh
Idle H H X X X X L L L H
Self-Refresh Entry Idle H L X X X X L L L H
Self-Refresh Exit
Idle
(S.R)
L
L
H X XX X H X X X
H X XX X L H H X
Clock Suspend
Mode Entry
Active
H
L X XX X X X X X
Power Down Mode Idle
Entry
Active (5)
H
H
L X XX X H X X X
L X XX X L H H X
Clock Suspend
Mode Exit
Active
L
H X XX X X X X X
Power Down Mode
Exit
Any
(Power
down)
L
L
H X XX X H X X X
H X XX X L H H X
Data Write/Output
Enable
Active
H
X L XX X X X X X
Data Write/Output
Disable
Active
H
X H XX X X X X X
Notes:
(1) V = Valid, X = Don't care, L = Low Level, H = High Level
(2) CKEn signal is input level when commands are provided.
(3) These are state of bank designated by BA signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
- 12 -

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