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D2-71683-LR Schematic ( PDF Datasheet ) - Intersil

Teilenummer D2-71683-LR
Beschreibung Intelligent Digital Amplifier and Sound Processor
Hersteller Intersil
Logo Intersil Logo 




Gesamt 30 Seiten
D2-71683-LR Datasheet, Funktion
Intelligent Digital Amplifier and Sound Processor
D2-7xx83
The D2-7xx83 family of the DAE-6™ Digital Audio Engine™
devices are complete System-on Chip (SoC) audio processor
and Class-D amplifier controllers. Integrated DSP processing
and configurable audio processing algorithms provide an
extremely flexible platform for feature rich and cost-effective
quality audio solutions which benefit from the addition of
Class-D amplifiers and DSP audio processing, meeting
demands of consumer electronics applications.
The 12 integrated digital PWM controllers can be used in a
variety of multi-channel audio system configurations,
supporting powered as well as line outputs. Fully protected
amplifier control provides efficient and clean Class-D power
output support.
The DAE-6™ device family supports full audio decoding for
formats including Dolby® Digital, Dolby® Pro Logic IIx,
AAC™ LC, DTS® Digital Surround, DTS® ES, and DTS Neo:6®.
The DAE-6 is pin-compatible and function/feature compatible
with the DAE-3™ devices, enabling additional decoding
capability to existing designs, or providing cost optimization to
lower-featured systems not requiring the additional audio
processing and decode capability.
Applications
• Audio Video Receiver (AVR)
• DTV Soundbar
• Home Theater in A Box (HTiB)
• Multi-Channel Multi-Media (MM) Systems
• Multi-Room Distributed Audio (MRDA)
• Powered Speaker Systems
• Automotive Trunk/Amplified Solutions
Features
• Advanced DAE-6™ Digital Audio Engine™ IC
- Pin Compatible and Function/Feature Compatible with
the D2Audio® DAE-3™ Device
• Total System on Chip (SoC)
- All Digital Class-D Amplifier Controller
- Full 5.1/7.1/9.1-Channel Amplifier Platform Support
• Enhanced Audio Processing Decoders
- Dolby® Digital/AC3
- Dolby® Pro Logic IIx
- AAC LC™
- DTS® Digital Surround
- DTS® ES
- DTS Neo:6®
• D2Audio® SoundSuite™ Enhancement and Virtualization
• Mark Levinson MightyCat™ Audio Enhancement
• Expanded On-Chip Memory Capacity
• Integrated DSP Processing
- 12 Channels of Digital Signal Processing (DSP) including
Equalizers, Filters, Mixers and Other Common Audio
Processing Blocks
- Fully Configurable and Routable Audio Signal Paths
• Flexible Audio Input and Output Configurations
• Embedded 8-Channel Sample Rate Converter
- Sample Rates from 32kHz up to 192kHz
• Real-Time Amplifier Control and Monitoring
- Supports Bridged, Half-Bridged, and Bridge-Tied Load
(BTL) Topologies, Using Discrete or Integrated Power
Stages from 10W to Over 500W
- Complete Fault Protection with Automatic Recovery
September 29, 2011
FN7838.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.






D2-71683-LR Datasheet, Funktion
D2-7xx83
Absolute Maximum Ratings (Note 6)
Supply Voltage
RVDD, PWMVDD, ADCVDD . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V
CVDD, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.4V
Input Voltage
Any Input but XTALI . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to RVDD +0.3V
XTALI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to PLLVDD +0.3V
Input Current, Any Pin but Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
128 Ld LQFP Package (Notes 4, 5) . . . . . .
40
6.5
Maximum Storage Temperature. . . . . . . . . . . . . . . . . . . . -55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +85°C
Digital I/O Supply Voltage, PWMVDD . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3V
Core Supply Voltage, CVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V
Analog Supply Voltage, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
6. Absolute Maximum parameters are not tested in production.
Electrical Specifications TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All
voltages referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. Minimum
supply currents are measured in full power down configuration.
SYMBOL
PARAMETER
TEST
MIN
MAX
CONDITIONS
(Note 10)
TYP
(Note 10) UNIT
VIH Digital Input High Logic Level (Note 7)
RVDD = 3.3V 2.0 -
(Scales with
RVDD)
-V
VIL Digital Input Low Logic Level (Note 7)
RVDD = 3.3V - - 0.8 V
(Scales with
RVDD)
VOH High Level Output Drive Voltage
(IOUT at - Pin Drive Strength Current, see “Pin Descriptions” on
page 12)
RVDD - 0.4
-
-V
VOL Low Level Output Drive Voltage
(IOUT at + Pin Drive Strength Current, see “Pin Descriptions” on
page 12)
- - 0.4 V
VIHX High Level Input Drive Voltage XTALI Pin
0.7
-
PLLVDD
V
VILX Low Level Input Drive Voltage XTALI Pin
- - 0.3 V
IIN
CIN
VOHO
Input Leakage Current (Note 8)
Input Capacitance
High Level Output Drive Voltage OSCOUT Pin
-
-
PLLVDD - 0.3
-
9
-
±10 µA
- pF
-V
VOLO Low Level Output Drive Voltage OSCOUT Pin
- - 0.3 V
COUT
tRST
RVDD/
PWMVDD
Output Capacitance
nRESET Pulse Width
Typical Digital and PWM I/O Pad Ring Supply
(Voltage)
(Current, Active)
- 9 - pF
- 10 - ns
3.0 3.3 3.6 V
- 15 - mA
(Current, Power-down)
- <1 - mA
CVDD Typical Core Supply
(Voltage)
1.7 1.8 1.9 V
(Current, Active)
- 450 - mA
PLLVDD Typical PLL Analog Supply
(Current, Power-down)
(Voltage)
- 15 - mA
1.7 1.8 1.9 V
(Current, Active)
- 25 - mA
(Current, Power-down)
- 10 - mA
6 FN7838.2
September 29, 2011

6 Page









D2-71683-LR pdf, datenblatt
D2-7xx83
Pin Descriptions
PIN
NAME
PIN (Note 14) TYPE
VOLTAGE
LEVEL
(V)
1 SC20 I/O
3.3
2 SRD2 I/O
3.3
3 SC21 I/O
3.3
4 SCK2 I/O
3.3
5 STD2 I/O
3.3
6 SC22 I/O
3.3
7 MCLK
O
3.3
8 SCK3
9 STD3
10 SC32
11 SC30
12 SC31
13 SRD3
14 STD0
15 SCK0
16 CVDD
17 CVDD
18 CGND
19 CGND
20 RGND
21 RVDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
P
P
P
P
P
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
22 SRD0
23 SC00
24 SC01
25 SC02
26 SCK
27 TIO1
I/O
I/O
I/O
I/O
I/O
I/O
3.3
3.3
3.3
3.3
3.3
3.3
28 MISO
29 MOSI
30 GPIO7
I/O
I/O
I/O
3.3
3.3
3.3
31 GPIO3
I/O
3.3
32 GPIO2
I/O
3.3
33 GPIO4
I/O
3.3
DRIVE
STRENGTH
(mA)
8
4
8
8
8
4
16
8
8
8
8
8
4
8
8
DESCRIPTION
Serial Audio Interface 2, I2S0 SCLK
Serial Audio Interface 2, I2S0 SDIN
Serial Audio Interface 2, I2S0 LRCK
Serial Audio Interface 2, I2S1 SCLK
Serial Audio Interface 2, I2S1 SDIN
Serial Audio Interface 2, I2S1 LRCK
I2S Serial Audio Master Clock output for external ADC/DAC components, drives low on reset
and is enabled by firmware assignment.
Serial Audio Interface 3, I2S3 SCLK
Serial Audio Interface 3, I2S3 SDIN
Serial Audio Interface 3, I2S3 LRCK
Serial Audio Interface 3, I2S2 SCLK
Serial Audio Interface 3, I2S2 LRCK
Serial Audio Interface 3, I2S2 SDIN
Serial Audio Interface 0, I2S SDAT0
Serial Audio Interface 0, I2S LRCK0
Core power, 1.8V
Core power, 1.8V
Core ground
Core ground
Digital pad ring ground. Internally connected to PWMGND.
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
4 Serial Audio Interface 0, SDIO, Defaults to input, and may be configured as GPIO by firmware.
8 Serial Audio Interface 0, SDIO, Defaults to input, and may be configured as GPIO by firmware.
8 Serial Audio Interface 0, I2S SDAT1
8 Serial Audio Interface 0, I2S LRCK1
4 SPI clock I/O with hysteresis input.
16 Timer I/O port 1. Operation and assignment is controlled by firmware. Leave unconnected
when not in use.
4 SPI master input, slave output data signal.
4 SPI master output, slave input data signal.
16 General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
16 General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
16 General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
16 General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
12 FN7838.2
September 29, 2011

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