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PDF ADP5054 Data sheet ( Hoja de datos )
| Número de pieza | ADP5054 | |
| Descripción | Quad Buck Regulator Integrated Power Solution | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
Wide input voltage range: 4.5 V to 15.5 V
±1.5% output accuracy over full temperature range
250 kHz to 2 MHz adjustable switching frequency with
individual ½× frequency option
Power regulation
Channel 1 and Channel 2
Programmable 2 A/4 A/6 A sync buck regulators with
low-side FET drivers
Channel 3 and Channel 4: 2.5 A sync buck regulators
Flexible parallel operation
Single 12 A output (Channel 1 and Channel 2 in parallel)
Single 5 A output (Channel 3 and Channel 4 in parallel)
Low 1/f noise density
40 µV rms at 0.8 VREF for 10 Hz to 100 kHz
Precision enable with 0.811 V accurate threshold
Active output discharge switch
FPWM/PSM mode selection
Frequency synchronization input or output
Power-good flag for Channel 1 output
UVLO, OCP, and TSD protection
48-lead, 7 mm × 7 mm LFCSP
−40°C to +125°C operational junctional temperature range
APPLICATIONS
FPGA and processor applications
Small cell base stations
Security and surveillance
Medical applications
GENERAL DESCRIPTION
The ADP5054 combines four high performance buck regulators in
a 48-lead LFCSP package that meets demanding performance and
board space requirements. The device enables direct connection
to high input voltages of up to 15.5 V with no preregulators.
Channel 1 and Channel 2 integrate high-side power MOSFETs and
low-side MOSFET drivers. External NFETs can be used in low-side
power devices to achieve an efficiency optimized solution and
to deliver a programmable output current of 2 A, 4 A, or 6 A.
Combining Channel 1 and Channel 2 in a parallel configuration
provides a single output with up to 12 A of current.
Channel 3 and Channel 4 integrate both high-side and low-side
MOSFETs to deliver an output current of 2.5 A. Combining
Channel 3 and Channel 4 in a parallel configuration can
provide a single output with up to 5 A of current.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Quad Buck Regulator
Integrated Power Solution
ADP5054
TYPICAL APPLICATION CIRCUIT
VREG
C1 VDD
C0
4.5V TO 15.5V
PVIN1
C2
COMP1
EN1
VREG
CFG12
(SS, 1/2 × fSW,
PARALLEL)
C5
PVIN2
COMP2
EN2
PWRGD
PVIN3
C8
COMP3
EN3
VREG
CFG34
(SS, 1/2 × fSW,
PARALLEL,
SCLKSET)
PVIN4
C11 COMP4
EN4
ADP5054
INTERNAL
VREG
100mA
OSCILLATOR
CHANNEL 1
BUCK
(2A/4A/6A)
VREG
CHANNEL 2
BUCK
(2A/4A/6A)
VREG
SYNC/MODE
RT
FB1
BST1
SW1
C3
DL1
Q1
PGND
DL2
SW2
Q2
BST2
FB2
C6
L1
L2
CHANNEL 3
BUCK
(2A)
BST3
SW3
C9
FB3
PGND3
L3
CHANNEL 4
BUCK
(2A)
BST4
SW4 C12
FB4
PGND4
L4
VOUT1
C4
VOUT2
C7
VOUT3
C10
VOUT4
C13
EXPOSED PAD
Figure 1.
The switching frequency of the ADP5054 can be programmed
or synchronized to an external clock from 250 kHz to 2 MHz,
and an individual ½× frequency configuration is available for
each channel.
The ADP5054 contains an individual precision enable pin on each
channel for easy power-up sequencing. The internal low 1/f noise
reference is implemented in the ADP5054 for noise sensitive
applications.
Table 1. Related Products
Model
Channels
I2C Package
ADP5050 Four bucks, one LDO
Yes 48-Lead LFCSP
ADP5051 Four bucks, supervisory Yes 48-Lead LFCSP
ADP5052 Four bucks, one LDO
No 48-Lead LFCSP
ADP5053 Four bucks, supervisory No 48-Lead LFCSP
ADP5054 Four high current bucks No 48-Lead LFCSP
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADP5054
BUCK REGULATOR SPECIFICATIONS
VIN = 12 V, VVREG = 5.0 V, fSW = 600 kHz for all channels, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C
for typical specifications, unless otherwise noted.
Table 3.
Parameter
CHANNEL 1 SYNC BUCK REGULATOR
FB1 Pin
Adjustable Feedback Voltage
Feedback Voltage Accuracy
Symbol
VFB1
VFB1(DEFAULT)
Feedback Bias Current
SW1 Pin
High-Side Power FET On Resistance
Current-Limit Threshold
IFB1
RDS(ON)_1H
ITH(ILIM1)
Minimum On Time
Minimum Off Time
Low-Side Driver, DL1 Pin
Rising Time
Falling Time
Sourcing Resistor
Sinking Resistor
Error Amplifier (EA), COMP1 Pin
EA Transconductance
Soft Start
Soft Start Time
Programmable Soft Start Range
Hiccup Time
COUT Discharge Switch On Resistance
CHANNEL 2 SYNC BUCK REGULATOR
FB2 Pin
Adjustable Feedback Voltage
Feedback Voltage Accuracy
tMIN_ON1
tMIN_OFF1
tRISING1
tFALLING1
tSOURCING1
tSINKING1
gm1
tSS1
tHICCUP1
RDIS1
VFB2
VFB2(DEFAULT)
Feedback Bias Current
SW2 Pin
High-Side Power FET On Resistance
Current-Limit Threshold
IFB2
RDS(ON)_2H
ITH(ILIM2)
Minimum On Time
Minimum Off Time
Low-Side Driver, DL2 Pin
Rising Time
Falling Time
Sourcing Resistor
Sinking Resistor
Error Amplifier (EA), COMP2 Pin
EA Transconductance
tMIN_ON2
tMIN_OFF2
tRISING2
tFALLING2
tSOURCING2
tSINKING2
gm2
Min
−0.55
−1.25
−1.5
5.2
2.6
7.8
310
2.0
−0.55
−1.25
−1.5
5.2
2.6
7.8
310
Typ Max
0.800
+0.55
+1.0
+1.5
0.1
50
6.9
3.8
10.4
115
1/9 × tSW
8.6
5.0
12.4
150
20
3.4
8
1.2
465 620
2.0
7 × tSS1
250
16.0
0.800
+0.55
+1.0
+1.5
0.1
50
6.9
3.8
10.4
115
1/9 × tSW
8.6
5.0
12.4
150
20
3.4
8
1.2
465 620
Unit Test Conditions/Comments
V
% TJ = 25°C
% 0°C ≤ TJ ≤ 85°C
% −40°C ≤ TJ ≤ +125°C
µA Adjustable voltage
mΩ Pin-to-pin measurement
A RILIM1 floating
A RILIM1 = 47 kΩ
A RILIM1 = 22 kΩ
ns fSW = 250 kHz to 2.0 MHz
ns fSW = 250 kHz to 2.0 MHz
ns CISS = 1.2 nF
ns CISS = 1.2 nF
Ω
Ω
µS
ms CFG12 connected to ground
ms
ms
Ω
V
% TJ = 25°C
% 0°C ≤ TJ ≤ +85°C
% −40°C ≤ TJ ≤ +125°C
µA Adjustable voltage
mΩ Pin-to-pin measurement
A RILIM2 = floating
A RILIM2 = 47 kΩ
A RILIM2 = 22 kΩ
ns fSW = 250 kHz to 2.0 MHz
ns fSW = 250 kHz to 2.0 MHz
ns CISS = 1.2 nF
ns CISS = 1.2 nF
Ω
Ω
µS
Rev. B | Page 5 of 31
5 Page 
Data Sheet
100
90
80
70
60
50
40
30
20
fSW = 250kHz
10 fSW = 600kHz
fSW = 1MHz
0
0 0.5 1.0 1.5 2.0 2.5
IOUT (A)
Figure 10. Channel 3/Channel 4 Efficiency Curve, VIN = 12 V, VOUT = 1.8 V,
FPWM Mode
100
90
80
70
60
50
40
30
20
10
0
01
VOUT = 1.2V FPWM
VOUT = 1.8V FPWM
VOUT = 3.3V FPWM
VOUT = 1.2V PWM/PSM
VOUT = 1.8V PWM/PSM
VOUT = 3.3V PWM/PSM
0.1 1 10
IOUT (A)
Figure 11. Channel 3/Channel 4 Efficiency Curve, VIN = 12 V, fSW = 600 kHz,
FPWM and Automatic PWM/PSM Modes
0.810
0.805
0.800
0.795
0.790
–50 –20
10
40
70 100 130
TEMPERATURE (°C)
Figure 12. 0.8 V Feedback Voltage Accuracy vs. Temperature
for Channel 1, Adjustable Output Model
ADP5054
750
700
650
600
550
500
450
–50
–20
10 40 70
TEMPERATURE (°C)
100 130
Figure 13. Frequency vs. Temperature, VIN = 12 V, fSW = 600 kHz
6.0
5.5
5.0
4.5
4.0
3.5
3.0
–50
0 50
TEMPERATURE (°C)
100
Figure 14. Quiescent Current vs. Temperature (Includes PVIN1, PVIN2,
PVIN3, and PVIN4)
50
45
40
35
30
25
20
15 VIN = 4.5V
VIN = 12V
VIN = 15V
10
–50 –20
10
40
70 100 130
TEMPERATURE (°C)
Figure 15. Shutdown Current vs. Temperature (EN1, EN2, EN3, and EN4 Low)
Rev. B | Page 11 of 31
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP5054.PDF ] | |
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