ADP223 Datasheet PDF - Analog Devices
| Part Number | ADP223 | |
| Description | High PSRR Voltage Regulators | |
| Manufacturers | Analog Devices | |
| Logo |  |
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Data Sheet
Dual, 300 mA Output, Low Noise,
High PSRR Voltage Regulators
ADP222/ADP223/ADP224/ADP225
FEATURES
Input voltage range: 2.5 V to 5.5 V
Small, 8-lead, 2 mm × 2 mm LFCSP package
Initial accuracy: ±1%
High PSRR: 70 dB at 10 kHz, 60 dB at 100 kHz, 40 dB at 1 MHz
Low noise: 27 µV rms at VOUT = 1.2 V, 50 µV rms at VOUT = 2.8 V
Excellent transient response
Low dropout voltage: 170 mV at 300 mA load
65 µA typical ground current at no load, both LDOs enabled
Fixed output voltage from 0.8 V to 3.3 V (ADP222/ADP224)
Adjustable output voltage range from 0.5 V to 5.0 V
(ADP223/ADP225)
Quick output discharge (QOD)—ADP224/ADP225
Overcurrent and thermal protection
APPLICATIONS
Portable and battery-powered equipment
Portable medical devices
Post dc-to-dc regulation
Point of sale terminals
Credit card readers
Automatic meter readers
Wireless network equipment
TYPICAL APPLICATION CIRCUITS
VIN = 4.2V
+ C1
1µF
R2
ON
OFF
ON
OFF
1 EN1
ADJ1 8
ADP223/
ADP225
2 EN2
VOUT1 7
3 GND
VIN 6
R1
VOUT2 = 2.0V
+ C2
1µF
4 ADJ2
VOUT2 5
VOUT1 = 2.8V
R3 + C3
1µF
R4
VIN = 4.2V
+ C1
1µF
ON
OFF
ON
OFF
Figure 1. ADP223/ADP225
1 EN1
SENSE1 8
ADP222/
ADP224
2 EN2
VOUT1 7
3 GND
VIN 6
4 SENSE2 VOUT2 5
VOUT1 = 1.5V
+ C2
1µF
VOUT2 = 3.3V
+ C3
1µF
GENERAL DESCRIPTION
The 300 mA, adjustable dual output ADP223/ADP225 and
fixed dual output ADP222/ADP224 combine high PSRR, low
noise, low quiescent current, and low dropout voltage in a
voltage regulator that is ideally suited for wireless applications
with demanding performance and board space requirements.
The ADP222/ADP224 are available with fixed outputs voltages
from 0.8V to 3.3V. The adjustable output ADP223/ADP225 may
be set to output voltages from 0.5 V to 5.0 V. The low quiescent
current, low dropout voltage, and wide input voltage range of
the ADP222/ADP223/ADP224/ADP225 extend the battery life
of portable devices.
The ADP222/ADP223/ADP224/ADP225 maintain power
supply rejection greater than 60 dB for frequencies as high as
Figure 2. ADP222/ADP224
100 kHz while operating with a low headroom voltage. The
ADP222/ADP223/ADP224/ADP225 offer much lower noise
performance than competing LDOs without the need for a
noise bypass capacitor. Overcurrent and thermal protection
circuitry prevent damage in adverse conditions.
The ADP224 and ADP225 are identical to the ADP222 and
ADP223, respectively, but with the addition of a quick output
discharge (QOD) feature.
The ADP222/ADP223/ADP224/ADP225 are available in a
small 8-lead, 2 mm × 2 mm LFCSP package and are stable with
tiny 1 µF, ±30% ceramic output capacitors, resulting in the smallest
possible board area for a wide variety of portable power needs.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
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Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
ADJ1, ADJ2, VOUT1, VOUT2 to GND
EN1, EN2 to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +6 V
−0.3 V to VIN
−0.3 V to +6 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
The ADP222/ADP223/ADP224/ADP225 can be damaged when
the junction temperature limits are exceeded. Monitoring
ambient temperature does not guarantee that TJ is within the
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may have to be derated. In applications with
moderate power dissipation and low PCB thermal resistance, the
maximum ambient temperature can exceed the maximum limit as
long as the junction temperature is within specification limits.
The junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (θJA). Maximum junction temperature (TJ) is calculated
from the ambient temperature (TA) and power dissipation (PD)
using the formula
TJ = TA + (PD × θJA)
ADP222/ADP223/ADP224/ADP225
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. θJA
is highly dependent on the application and board layout. In
applications where high maximum power dissipation exists,
close attention to thermal board design is required. The value
of θJA may vary, depending on PCB material, layout, and
environmental conditions. The specified value of θJA is based
on a 4-layer, 4 in × 3 in, 2½ oz copper board, as per JEDEC
standards. For more information, see the AN-772 Application
Note, A Design and Manufacturing Guide for the Lead Frame
Chip Scale Package (LFCSP).
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation from
the package, factors that make ΨJB more useful in real-world
applications. Maximum junction temperature (TJ) is calculated
from the board temperature (TB) and power dissipation (PD)
using the formula
TJ = TB + (PD × ΨJB)
Refer to JESD51-8 and JESD51-12 for more detailed
information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
8-Lead 2 mm × 2 mm LFCSP
θJA θJC ΨJB Unit
50.2 31.7 18.2 °C/W
ESD CAUTION
Rev. B | Page 5 of 24
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