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PDF ADG5462F Data sheet ( Hoja de datos )
| Número de pieza | ADG5462F | |
| Descripción | Quad Channel Protector | |
| Fabricantes | Analog Devices | |
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Data Sheet
User Defined Fault Protection and
Detection,10 Ω RON, Quad Channel Protector
ADG5462F
FEATURES
User defined secondary supplies set overvoltage level
Overvoltage protection up to −55 V and +55 V
Power-off protection up to −55 V and +55 V
Overvoltage detection on source pins
Minimum secondary supply level: 4.5 V single-supply
Interrupt flag indicates fault status
Low on resistance: 10 Ω typical
On-resistance flatness: 0.5 Ω maximum
4 kV human body model (HBM) ESD rating
Latch-up immune under any circumstance
VSS to VDD analog signal range
±5 V to ±22 V dual supply operation
8 V to 44 V single-supply operation
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
APPLICATIONS
Analog input/output modules
Process control/distributed control systems
Data acquisition
Instrumentation
Avionics
Automatic test equipment
Communication systems
GENERAL DESCRIPTION
The ADG5462F contains four channels that are overvoltage
protected. The channel protector is placed in series with the signal
path and protects sensitive components from overvoltage faults
in that path. The channel protector prevents overvoltages when
powered and unpowered, and it is ideal for use in applications
where correct power supply sequencing cannot always be guaranteed.
The primary supply voltages define the on-resistance profile,
while the secondary supply voltages define the voltage level at
which the overvoltage protection engages.
When no power supplies are present, the channel remains in the off
condition, and the channel inputs are high impedance. Under
normal operating conditions, if the analog input signal levels on
any Sx pin exceed positive fault voltage (POSFV) or negative fault
voltage (NEGFV) by a threshold voltage (VT), the channel turns
off and that Sx pin becomes high impedance. If the DR pin is
driven low, the drain pin (Dx) is pulled to the secondary supply
voltage that was exceeded. The output profile for each DR voltage
level is shown in Figure 49. Input signal levels up to −55 V or
+55 V relative to ground are blocked in both the powered and
unpowered conditions.
FUNCTIONAL BLOCK DIAGRAM
VDD VSS
S1 D1
S2 D2
S3 D3
S4
VIN
D4
VOUT
ADG5462F FF
POSFV NEGFV DR
Figure 1.
The low on-resistance of these switches, combined with the
on-resistance flatness over a significant portion of the signal
range make them an ideal solution for data acquisition and
instrumentation applications where excellent linearity and low
distortion are critical.
PRODUCT HIGHLIGHTS
1. Source pins (Sx) are protected against voltages greater than
the secondary supply rails (POSFV and NEGFV), up to
−55 V and +55 V.
2. In an unpowered state, source pins (Sx) are protected
against voltages from −55 V to +55 V.
3. Overvoltage detection with digital output indicates the
operating state of the channels.
4. Trench isolation guards against latch-up.
5. Optimized for low on-resistance and on-resistance flatness.
6. The ADG5462F operates from a dual power supply range of
±5 V to ±22 V or a single power supply range of 8 V to 44 V.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADG5462F
±20 V DUAL SUPPLY
VDD = 20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
Power Supplies Grounded
Power Supplies Floating
DIGITAL INPUTS/OUTPUTS
Input Voltage High, VINH
Input Voltage Low, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
Output Voltage High, VOH
Output Voltage Low, VOL
−40°C to −40°C to
+25°C +85°C +125°C Unit
10
11.5 14.5
9.5
11 14
0.05
0.35 0.5
0.05
0.35 0.5
1.0
1.4 1.5
0.1
0.4 0.5
0.7
VDD to VSS
16.5
16.5
0.5
0.5
1.5
0.5
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
±0.3 nA typ
±1.5 ±2.0 ±4.5 nA max
±78 µA typ
±40 µA typ
±5.0
±1.0 ±1.0
±10
±30 ±50
±10 ±10
0.7
5.0
2.0
0.8
±1.0
±100
±10
nA typ
µA max
nA typ
nA max
µA typ
2.0 V min
0.8 V max
µA typ
1.2 µA max
pF typ
V min
V max
Test Conditions/Comments
VDD = +18 V, VSS = −18 V, see Figure 35
VS = ±15 V, IS = −10 mA
VS = ±13.5 V, IS = −10 mA
VS = ±15 V, IS = −10 mA
VS = ±13.5 V, IS = −10 mA
VS = ±15 V, IS = −10 mA
VS = ±13.5 V, IS = −10 mA
See Figure 23
VDD = +22 V, VSS = −22 V
VS = VD = ±15 V, see Figure 36
VDD = +22 V, VSS = −22 V, GND = 0 V,
VS = ±55 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, VS = ±55 V,
see Figure 38
DR = floating or VDD
VDD = +22 V, VSS = −22 V, GND = 0 V,
VS = ±55 V, see Figure 37
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±55 V, see Figure 38
VDD = floating, VSS = floating, GND = 0 V,
VS = ±55 V, see Figure 38
VIN = VGND or VDD
Rev. B | Page 5 of 29
5 Page 
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
POSFV to GND
NEGFV to GND
Sx Pins to GND
Sx to VDD or VSS
VS to VD
Dx Pins1, 2 to GND
Digital Input (DR pin) to GND
Peak Current, Sx or Dx Pins
Continuous Current, Sx or Dx Pins
Digital Output (FF pin)
Dx Pins, Overvoltage State,
DR = GND, Load Current
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Thermal Impedance, θJA
16-Lead TSSOP (4-Layer Board)
16-Lead LFCSP (4-Layer Board)
Reflow Soldering Peak
Temperature, Pb-Free
ESD (HBM: ESDA/JEDEC JS-001-2011)
Input/Output Port to Supplies
Input/Output Port to
Input/Output Port
All Other Pins
Rating
48 V
−0.3 V to +48 V
−48 V to +0.3 V
−0.3 V to VDD + 0.3 V
VSS − 0.3V to +0.3 V
−55 V to +55 V
80 V
80 V
NEGFV − 0.7 V to POSFV +
0.7 V or 30 mA, whichever
occurs first
GND − 0.7V to 48 V or 30 mA,
whichever occurs first
288 mA (pulsed at 1 ms,
10% duty cycle maximum)
Data3 + 15%
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
1 mA
−40°C to +125°C
−65°C to +150°C
150°C
112.6°C/W
30.4°C/W
As per JEDEC J-STD-020
4 kV
4 kV
4 kV
1 Overvoltages at the Dx pins are clamped by internal diodes. Limit current to
the maximum ratings given.
2 POSFV and NEGFV must not exceed VDD and VSS, respectively.
3 See Table 5.
ADG5462F
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
Rev. B | Page 11 of 29
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet ADG5462F.PDF ] | |
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