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AD9154 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9154
Beschreibung Digital-to-Analog Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9154 Datasheet, Funktion
Data Sheet
Quad, 16-Bit, 2.4 GSPS, TxDAC+®
Digital-to-Analog Converter
AD9154
FEATURES
Supports input data rates up to 1 GSPS
Proprietary, low spurious and distortion design
Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at
180 MHz IF
Six carrier GSM IMD = 78 dBc, 600 kHz carrier spacing at
180 MHz IF
SFDR = 72 dBc at 180 MHz IF, −6 dBFS single tone
Flexible 8-lane JESD204B interface
Multiple chip synchronization
Fixed latency
Data generator latency compensation
Input signal power detection
High performance, low noise phase-locked loop (PLL) clock
multiplier
Digital inverse sinc filter
Digital quadrature modulation using a numerically
controlled oscillator (NCO)
Nyquist band selection—mix mode
Selectable 1×, 2×, 4×, and 8× interpolation filters
Low power: 2.11 W at 1.6 GSPS, full operating conditions
88-lead, exposed pad LFCSP
APPLICATIONS
Wireless communications
Multicarrier LTE and GSM base stations
Wideband repeaters
Software defined radios
Wideband communications
Point to point microwave radio
Transmit diversity, multiple input/multiple output (MIMO)
Instrumentation
Automated test equipment
GENERAL DESCRIPTION
The AD9154 is a quad, 16-bit, high dynamic range digital-to-
analog converter (DAC) that provides a maximum sample rate
of 2.4 GSPS, permitting multicarrier generation up to the Nyquist
frequency in baseband mode. The AD9154 includes features
optimized for direct conversion transmit applications, including
complex digital modulation, input signal power detection, and
gain, phase, and offset compensation. The DAC outputs are
optimized to interface seamlessly with the ADRF6720-27 radio
frequency quadrature modulator (AQM) from Analog Devices,
Inc. In mix mode, the AD9154 DAC can reconstruct carriers in
the second and third Nyquist zones. A serial port interface (SPI)
provides the programming/readback of internal parameters.
The full-scale output current can be programmed over a range
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
QUAD MOD
ADRF6720-27
DAC
RF
OUTPUT
0°/90° PHASE
SHIFTER
LPF
DAC
JESD204B
SYNCOUTx±
SYSREF
LO_IN
MOD_SPI
QUAD MOD
ADRF6720-27
QUAD DAC
DAC
RF
OUTPUT 1
0°/90° PHASE
SHIFTER
LPF
LO_IN
DAC
AD9154
MOD_SPI
DAC DAC
CLOCK SPI
Figure 1.
JESD204B
SYNCOUTx±
of 4 mA to 20 mA. The AD9154 is available in two different
88-lead LFCSP packages.
PRODUCT HIGHLIGHTS
1. Ultrawide signal bandwidth enables emerging wideband
and multiband wireless applications.
2. Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
3. JESD204B Subclass 1 support simplifies multichip
synchronization.
4. Small package size with a 12 mm × 12 mm footprint.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD9154 Datasheet, Funktion
AD9154
Data Sheet
DIGITAL SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input Voltage (VIN) Logic
High
Low
CMOS OUTPUT LOGIC LEVEL
Output Voltage (VOUT) Logic
High
Low
MAXIMUM DAC UPDATE RATE1
ADJUSTED DAC UPDATE RATE
INTERFACE4
Number of JESD204B Lanes
JESD204B Serial Interface Speed
Minimum
Maximum
DAC CLOCK INPUT (CLK±)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate, DAC Clock
Sourced Directly from CLK±
PLL Multiplier Mode Clock Input
Frequency5
SYSREF INPUT (SYSREF±)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
SYSREF± Frequency6
SYSREF± TO DAC CLOCK7
Setup Time
Hold Time
SPI
Maximum Clock Rate
Minimum SCLK Pulse Width
High
Low
SDIO to SCLK
Setup Time
Hold Time
SDO to SCLK
Data Valid Window
Symbol
tSSD
tHSD
SCLK
tPWH
tPWL
tDS
tDH
tDV
Test Conditions/Comments
1.8 V IOVDD 3.3 V
1.8 V IOVDD 3.3 V
1.8 V IOVDD 3.3 V
1.8 V IOVDD 3.3 V
1× interpolation2 (see Table 4)
2× interpolation3
4× interpolation
8× interpolation
1× interpolation
2× interpolation
4× interpolation
8× interpolation
Per lane
Per lane, SVDD12 = 1.3 V ± 2%
Self biased input, ac-coupled
6.0 GHz ≤ fVCO ≤ 12.0 GHz
SYSREF± differential swing = 0.4 V,
slew rate = 1.3 V/ns, (ac-coupled, and
0 V, 0.6 V, 1.25 V, 2.0 V dc-coupled
common-mode voltages)
See timing diagrams shown in
Figure 39 and Figure 40
IOVDD = 1.8 V
Rev. B | Page 6 of 124
Min Typ
0.7 × IOVDD
0.7 × IOVDD
1096
2192
2400
2400
1096
1096
600
300
8
10.96
400
2400
35
1000
600
400 1000
0
111
145
10
5
2
25
Max
0.3 × IOVDD
0.3 × IOVDD
1.44
2000
1000
2000
2000
fDATA/(K × (F/S))
8
12
Unit
V
V
V
V
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
Lanes
Gbps
Gbps
mV
mV
MHz
MHz
mV
mV
Hz
ps
ps
MHz
ns
ns
ns
ns
ns

6 Page









AD9154 pdf, datenblatt
AD9154
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PVDD12 1
CLK+ 2
CLK– 3
PVDD12 4
SYSREF+ 5
SYSREF– 6
PVDD12 7
PVDD12 8
PVDD12 9
PVDD12 10
TXEN0 11
TXEN1 12
DVDD12 13
DVDD12 14
SERDIN0+ 15
SERDIN0– 16
SVDD12 17
SERDIN1+ 18
SERDIN1– 19
SVDD12 20
VTT 21
SVDD12 22
AD9154
TOP VIEW
(Not to Scale)
66 IOVDD
65 CS
64 SCLK
63 SDIO
62 SDO
61 RESET
60 IRQ
59 PDP OUT0
58 PDP OUT1
57 PVDD12
56 PVDD12
55 DNC
54 DNC
53 DVDD12
52 SERDIN7+
51 SERDIN7–
50 SVDD12
49 SERDIN6+
48 SERDIN6–
47 SVDD12
46 VTT
45 SVDD12
Data Sheet
NOTES
1. THE EXPOSED PAD MUST BE SECURELY CONNECTED TO THE GROUND PLANE.
2. DNC = DO NOT CONNECT.
Figure 3. Pin Configuration
Table 12. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 4, 7, 8, 9, 10, PVDD12
56, 57
1.2 V Clock Supplies.
2
CLK+
PLL Reference/Clock Input, Positive. When the PLL is used, this pin is the positive reference clock input.
When the PLL is not used, this pin is the positive device clock input. This pin is self biased and must be
ac-coupled.
3
CLK−
PLL Reference/Clock Input, Negative. When the PLL is used, this pin is the negative reference clock input.
When the PLL is not used, this pin is the negative device clock input. This pin is self biased and must be
ac-coupled.
5
SYSREF+
Timing Reference Input, Positive. This pin is used in JESD204B Subclass 1 systems and is self biased,
ac-coupled, or dc-coupled.
6
SYSREF−
Timing Reference Input, Negative. This pin is used in JESD204B Subclass 1 systems and is self biased,
ac-coupled, or dc-coupled.
11
TXEN0
Transmit enable for DAC0 and DAC1. CMOS levels are determined with respect to IOVDD.
12
TXEN1
Transmit Enable for DAC2 and DAC3. CMOS levels are determined with respect to IOVDD.
13, 14, 53
DVDD12
1.2 V Digital Supplies.
15
SERDIN0+
Serial Channel Input 0, Positive. CML compliant. SERDIN0+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
16
SERDIN0−
Serial Channel Input 0, Negative. CML compliant. SERDIN0− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
17, 20, 22, 28,
31, 32, 33, 36,
39, 45, 47, 50
SVDD12
1.2 V JESD204B Receiver Supplies.
18
SERDIN1+
Serial Channel Input 1, Positive. CML compliant. SERDIN1+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
19
SERDIN1−
Serial Channel Input 1, Negative. CML compliant. SERDIN1− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
21, 25, 42, 46 VTT
1.2 V Termination Voltage Pins.
Rev. B | Page 12 of 124

12 Page





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