AD5761R Datasheet PDF - Analog Devices
| Part Number | AD5761R | |
| Description | Bipolar/Unipolar Voltage Output DACs | |
| Manufacturers | Analog Devices | |
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Data Sheet
Multiple Range, 16-/12-Bit, Bipolar/Unipolar
Voltage Output DACs with 2 ppm/°C Reference
AD5761R/AD5721R
FEATURES
GENERAL DESCRIPTION
8 software-programmable output ranges: 0 V to 5 V, 0 V to 10 V,
0 V to 16 V, 0 V to 20 V, ±3 V, ±5 V, ±10 V, and −2.5 V to +7.5 V;
5% overrange
Low drift 2.5 V reference: ±2 ppm/°C typical
Total unadjusted error (TUE): 0.1% FSR maximum
16-bit accuracy: ±2 LSB maximum
Guaranteed monotonicity: ±1 LSB maximum
Single channel, 16-/12-bit DACs
Settling time: 7.5 μs typical
Integrated reference buffers
Low noise: 35 nV/√Hz
Low glitch: 1 nV-sec (0 V to 5 V range)
1.7 V to 5.5 V digital supply range
Asynchronous updating via LDAC
Asynchronous RESET to zero scale/midscale
DSP-/microcontroller-compatible serial interface
Robust 4 kV HBM ESD rating
16-lead, 3 mm × 3 mm LFCSP package
16-lead TSSOP package
Operating temperature range: −40°C to +125°C
APPLICATIONS
The AD5761R/AD5721R are single channel, 16-/12-bit serial
input, voltage output, digital-to-analog converters (DACs).
They operate from single supply voltages from 4.75 V to 30 V
or dual supply voltages from −16.5 V to 0 V VSS and 4.75 V to
16.5 V VDD. The integrated output amplifier, reference buffer,
and reference provide a very easy to use, universal solution.
The devices offer guaranteed monotonicity, integral nonlinearity
(INL) of ±2 LSB maximum, 35 nV/√Hz noise, and 7.5 μs settling
time on selected ranges.
The AD5761R/AD5721R use a serial interface that operates at
clock rates of up to 50 MHz and are compatible with DSP and
microcontroller interface standards. Double buffering allows the
asynchronous updating of the DAC output. The input coding
is user-selectable twos complement or straight binary. The
asynchronous reset function resets all registers to their default
state. The output range is user selectable, via the RA[2:0] bits
in the control register.
The devices available in a 3 mm × 3 mm LFCSP package and a
16-lead TSSOP package offer guaranteed specifications over the
−40°C to +125°C industrial temperature range.
Industrial automation
Instrumentation, data acquisition
Open-/closed-loop servo control, process control
Programmable logic controllers
FUNCTIONAL BLOCK DIAGRAM
VDD
VREFIN/VREFOUT
DVCC
ALERT
SDI
SCLK
SYNC
SDO
RESET
CLEAR
AD5761R/AD5721R
2.5V
REFERENCE
REFERENCE
BUFFERS
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
12/16
INPUT
REG
DAC 12/16
REG
12-BIT/
16-BIT
DAC
NOTES
DNC
DGND VSS
LDAC
AGND
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 1.
VOUT
0V TO 5V
0V TO 10V
0V TO 16V
0V TO 20V
±3V
±5V
±10V
−2.5V TO +7.5V
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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Data Sheet
AD5761R/AD5721R
Parameter2
LOGIC OUTPUTS (SDO, ALERT)5
Output Voltage
Low, VOL
High, VOH
High Impedance, SDO Pin
Leakage Current
Pin Capacitance
POWER REQUIREMENTS
VDD
VSS
DVCC
IDD
ISS
DICC
Power Dissipation
DC Power Supply Rejection
Ratio (PSRR)5
AC PSRR5
Min Typ Max
DVCC − 0.5
0.4
−1 +1
5
4.75
−16.5
1.7
5.1
1
0.005
67.1
0.1
30
0
5.5
6.5
3
1
0.1
65
65
80
80
Unit
V
V
µA
pF
V
V
V
mA
mA
µA
mW
mV/V
mV/V
dB
dB
dB
dB
Test Conditions/Comments
DVCC = 1.7 V to 5.5 V, sinking 200 µA
DVCC = 1.7 V to 5.5 V, sourcing 200 µA
Outputs unloaded, external reference
Outputs unloaded
VIH = DVCC, VIL = DGND
±11 V operation, outputs unloaded, TSSOP package
VDD ± 10%, VSS = −15 V
VSS ±10%, VDD = +15 V
VDD ±200 mV, 50 Hz/60 Hz, VSS = −15 V, internal
reference, CLOAD = 100 nF
VSS ±200 mV, 50 Hz/60 Hz, VDD = +15 V, internal
reference, CLOAD = 100 nF
VDD ±200 mV, 50 Hz/60 Hz, VSS = −15 V, external
reference, CLOAD = unloaded
VSS ±200 mV, 50 Hz/60 Hz, VDD = +15 V, external
reference, CLOAD = unloaded
1 For specified performance, headroom requirement is 1 V.
2 Temperature range: −40°C to +125°C, typical at +25°C.
3 External reference means 2 V to 2.85 V with overrange and 2 V to 3 V without overrange.
4 Integral nonlinearity error is specified at ±4 LSB (min/max) for 16 V and 20 V ranges with VREFIN/VREFOUT = 2.5 V external and internal, and for all ranges with VREFIN/VREFOUT =
2 V to 2.85 V with overrange and 2 V to 3 V without overrange.
5 Guaranteed by design and characterization, not production tested.
Rev. A | Page 5 of 35
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