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PDF AD5672R Data sheet ( Hoja de datos )
| Número de pieza | AD5672R | |
| Descripción | 12-/16-Bit nanoDAC+ | |
| Fabricantes | Analog Devices | |
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Data Sheet
Octal, 12-/16-Bit nanoDAC+ with
2 ppm/°C Reference, SPI Interface
AD5672R/AD5676R
FEATURES
GENERAL DESCRIPTION
High performance
High relative accuracy (INL): ±3 LSB maximum at 16 bits
Total unadjusted error (TUE): ±0.14% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.06% of FSR maximum
Low drift 2.5 V reference: 2 ppm/°C typical
Wide operating ranges
−40°C to +125°C temperature range
2.7 V to 5.5 V power supply range
Easy implementation
User selectable gain of 1 or 2 (GAIN pin/gain bit)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Robust 2 kV HBM and 1.5 kV FICDM ESD rating
20-lead, RoHS-compliant TSSOP and LFCSP
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC input/output cards)
Industrial automation
Data acquisition systems
The AD5672R/AD5676R are low power, octal, 12-/16-bit buffered
voltage output digital-to-analog converters (DACs). They include
a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a
gain select pin giving a full-scale output of 2.5 V (gain = 1) or
5 V (gain = 2). The devices operate from a single 2.7 V to 5.5 V
supply and are guaranteed monotonic by design. The AD5672R/
AD5676R are available in a 20-lead TSSOP and in a 20-lead LFCSP
and incorporate a power-on reset circuit and a RSTSEL pin that
ensures that the DAC outputs power up to zero scale or midscale
and remain there until a valid write. The AD5672R/AD5676R
contain a power-down mode, reducing the current consumption to
1 µA typical while in power-down mode.
Table 1. Octal nanoDAC+® Devices
Interface
Reference
16-Bit
SPI
Internal
AD5676R
External
AD5676
I2C
Internal
AD5675R
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5672R (12-bit): ±1 LSB maximum.
AD5676R (16-bit): ±3 LSB maximum.
2. Low Drift, 2.5 V On-Chip Reference.
12-Bit
AD5672R
Not applicable
AD5671R
FUNCTIONAL BLOCK DIAGRAM
VLOGIC
VDD
VREFOUT
AD5672R/AD5676R
SCLK
SYNC
SDI
SDO
LDAC
RESET
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
2.5V
REF
STRING
DAC 0
BUFFER
STRING
DAC 1
BUFFER
STRING
DAC 2
BUFFER
STRING
DAC 3
BUFFER
STRING
DAC 4
BUFFER
STRING
DAC 5
BUFFER
STRING
DAC 6
BUFFER
STRING
DAC 7
BUFFER
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
POWER-ON
RESET
GAIN POWER-DOWN
×1/×2
LOGIC
RSTSEL
Figure 1.
GAIN
GND
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD5672R/AD5676R
AD5676R SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ, CL = 200 pF, all specifications TA = −40°C to +125°C, unless otherwise noted.
Table 3.
Parameter
STATIC PERFORMANCE1
Resolution
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Zero Code Error
Offset Error
Full-Scale Error
Gain Error
TUE
Offset Error Drift2
DC Power Supply Rejection
Ratio (PSRR)2
DC Crosstalk2
Min
16
A Grade
Typ Max
Min
±1.8
±1.7
±0.7
±0.5
0.8
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
±0.03
±0.006
±1
0.25
±8
±8
±1
±1
3
±6
±4
±0.28
±0.14
±0.24
±0.12
±0.3
±0.25
16
±2
B Grade
Typ Max
Unit
±1.8
±1.7
±0.7
±0.5
0.8
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
±0.03
±0.006
±1
0.25
±3
±3
±1
±1
1.6
±2
±1.5
±0.14
±0.07
±0.12
±0.06
±0.18
±0.14
Bits
LSB
LSB
LSB
LSB
mV
mV
mV
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
mV/V
±2 µV
OUTPUT CHARACTERISTICS2
Output Voltage Range
Output Current Drive
Capacitive Load Stability
Resistive Load3
Load Regulation
0
0
1
±3
±2
2.5
5
15
2
10
183
0
0
1
±3 µV/mA
±2 µV
2.5 V
5V
15 mA
2 nF
10 nF
kΩ
183 µV/mA
177 177 µV/mA
Short-Circuit Current4
Load Impedance at Rails5
Power-Up Time
REFERENCE OUTPUT
Output Voltage6
Reference Temperature
Coefficient7, 8
Output Impedance2
Output Voltage Noise2
Output Voltage Noise Density2
2.4975
40
25
2.5
5
0.04
13
240
40
25
2.5
2.5025 2.4975
20
2
0.04
13
240
mA
Ω
µs
2.5025 V
5 ppm/°C
Ω
µV p-p
nV/√Hz
Load Regulation Sourcing2
Load Regulation Sinking2
Output Current Load
Capability2
Line Regulation2
Long-Term Stability/Drift2
Thermal Hysteresis2
29 29
74 74
±20 ±20
43 43
12 12
125 125
25 25
Rev. B | Page 5 of 34
µV/mA
µV/mA
mA
µV/V
ppm
ppm
ppm
Test Conditions/Comments
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1 or gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
DAC code = midscale, VDD =
5 V ± 10%
Due to single channel, full-scale
output change
Due to load current change
Due to powering down (per channel)
Gain = 1
Gain = 2
RL = ∞
RL = 1 kΩ
VDD = 5 V ± 10%, DAC code =
midscale, −30 mA ≤ IOUT ≤ +30 mA
VDD = 3 V ± 10%, DAC code =
midscale, −20 mA ≤ IOUT ≤ +20 mA
Exiting power-down mode, VDD = 5 V
See the Terminology section
0.1 Hz to 10 Hz
At ambient temperature, f = 10 kHz,
CL = 10 nF, gain = 1 or 2
At ambient temperature
At ambient temperature
VDD ≥ 3 V
At ambient temperature
After 1000 hours at 125°C
First cycle
Additional cycles
5 Page 
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 7.
Parameter
VDD to GND
VLOGIC to GND
VOUTx to GND
VREF to GND
Digital Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak Temperature,
Pb-Free (J-STD-020)
ESD Ratings
Human Body Model (HBM)
Field-Induced Charged Device Model
(FICDM)
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−40°C to +125°C
−65°C to +150°C
125°C
260°C
2 kV
1.5 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
AD5672R/AD5676R
THERMAL RESISTANCE
The design of the thermal board requires close attention. Thermal
resistance is highly impacted by the printed circuit board (PCB)
being used, layout, and environmental conditions.
Table 8. Thermal Resistance
Package Type θJA θJB θJC ΨJT ΨJB Unit
20-Lead TSSOP 98.65 44.39 17.58 1.77 43.9 °C/W
(RU-20)1
20-Lead LFCSP 82
(CP-20-8)2
16.67 32.5 0.43 22 °C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD51
2 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with nine thermal vias. See JEDEC JESD51.
ESD CAUTION
Rev. B | Page 11 of 34
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD5672R.PDF ] | |
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