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EFM8BB1 Schematic ( PDF Datasheet ) - Silicon Laboratories

Teilenummer EFM8BB1
Beschreibung microcontrollers
Hersteller Silicon Laboratories
Logo Silicon Laboratories Logo 




Gesamt 30 Seiten
EFM8BB1 Datasheet, Funktion
EFM8 Busy Bee Family
EFM8BB1 Data Sheet
The EFM8BB1, part of the Busy Bee family of MCUs, is a multi-
purpose line of 8-bit microcontrollers with a comprehensive feature
set in small packages.
These devices offer high-value by integrating advanced analog and communication pe-
ripherals into small packages, making them ideal for space-constrained applications.
With an efficient 8051 core, enhanced pulse-width modulation, and precision analog, the
EFM8BB1 family is also optimal for embedded applications.
EFM8BB1 applications include the following:
• Motor control
• Consumer electronics
• Sensor controllers
• Medical equipment
• Lighting systems
• I/O port expander
KEY FEATURES
• Pipelined 8-bit C8051 core with 25 MHz
maximum operating frequency
• Up to 18 multifunction, 5 V tolerant I/O pins
• One 12-bit Analog to Digital converter
(ADC)
• Two low-current analog comparators
• Integrated temperature sensor
• 3-channel enhanced PWM / PCA
• Four 16-bit timers
• UART, SPI and SMBus/I2C
• Priority crossbar for flexible pin mapping
Core / Memory
CIP-51 8051 Core
(25 MHz)
Clock Management
External CMOS
Oscillator
High Frequency
RC Oscillator
Energy Management
Internal LDO
Regulator
Power-On Reset
Flash Program
Memory
(up to 8 KB)
RAM Memory
(up to 512 bytes)
Debug Interface
with C2
Serial Interfaces
UART
SPI
I2C / SMBus
I/O Ports
External
Interrupts
Pin Reset
General Purpose I/O
Low Frequency
RC Oscillator
8-bit SFR bus
Timers and Triggers
16-bit
Timers
PCA/PWM
Watchdog Timer
Brown-Out Detector
Analog Interfaces
ADC
Analog
Comparators
Internal Voltage Reference
Security
16-bit CRC
Lowest power mode with peripheral operational:
Normal
Idle
Shutdown
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Rev. 1.1






EFM8BB1 Datasheet, Funktion
3.5 Counters/Timers and PWM
EFM8BB1 Data Sheet
System Overview
Programmable Counter Array (PCA0)
The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU
intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare mod-
ule for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking options.
Each capture/compare module may be configured to operate independently in one of five modes: Edge-Triggered Capture, Software
Timer, High-Speed Output, Frequency Output, or Pulse-Width Modulated (PWM) Output. Each capture/compare module has its own
associated I/O line (CEXn) which is routed through the crossbar to port I/O when enabled.
• 16-bit time base
• Programmable clock divisor and clock source selection
• Up to three independently-configurable channels
• 8, 9, 10, 11 and 16-bit PWM modes (center or edge-aligned operation)
• Output polarity control
• Frequency output mode
• Capture on rising, falling or any edge
• Compare function for arbitrary waveform generation
• Software timer (internal compare) mode
• Can accept hardware “kill” signal from comparator 0
Timers (Timer 0, Timer 1, Timer 2, and Timer 3)
Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and
the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time inter-
vals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary
modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities.
Timer 0 and Timer 1 include the following features:
• Standard 8051 timers, supporting backwards-compatibility with firmware and hardware.
• Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin.
• 8-bit auto-reload counter/timer mode
• 13-bit counter/timer mode
• 16-bit counter/timer mode
• Dual 8-bit counter/timer mode (Timer 0)
Timer 2 and Timer 3 are 16-bit timers including the following features:
• Clock sources include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8.
• 16-bit auto-reload timer mode
• Dual 8-bit auto-reload timer mode
• External pin capture (Timer 2)
• LFOSC0 capture (Timer 3)
Watchdog Timer (WDT0)
The device includes a programmable watchdog timer (WDT) running off the low-frequency oscillator. A WDT overflow forces the MCU
into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences
a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following
a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by
system software or locked on to prevent accidental disabling. Once locked, the WDT cannot be disabled until the next system reset.
The state of the RST pin is unaffected by this reset.
The Watchdog Timer has the following features:
• Programmable timeout interval
• Runs from the low-frequency oscillator
• Lock-out feature to prevent any modification until a system reset
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EFM8BB1 pdf, datenblatt
EFM8BB1 Data Sheet
Electrical Specifications
Parameter
Symbol Test Condition
Min Typ Max Unit
Note:
1. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the functions increa-
ses supply current by the specified amount.
2. Includes supply current from internal regulator, supply monitor, and High Frequency Oscillator.
3. Includes supply current from internal regulator, supply monitor, and Low Frequency Oscillator.
4. ADC0 always-on power excludes internal reference supply current.
5. The internal reference is enabled as-needed when operating the ADC in burst mode to save power.
Table 4.3. Reset and Supply Monitor
Parameter
Symbol
VDD Supply Monitor Threshold
VVDDM
Power-On Reset (POR) Threshold VPOR
VDD Ramp Time
tRMP
Reset Delay from POR
tPOR
Reset Delay from non-POR source tRST
RST Low Time to Generate Reset tRSTL
Missing Clock Detector Response tMCD
Time (final rising edge to reset)
Missing Clock Detector Trigger
Frequency
FMCD
VDD Supply Monitor Turn-On Time tMON
Test Condition
Rising Voltage on VDD
Falling Voltage on VDD
Time to VDD ≥ 2.2 V
Relative to VDD ≥ VPOR
Time between release of reset
source and code execution
FSYSCLK > 1 MHz
Table 4.4. Flash Memory
Min Typ Max
1.85 1.95
2.1
— 1.4 —
0.75 — 1.36
10 — —
3 10 31
— 39 —
15 — —
0.625
1.2
— 7.5 13.5
—2—
Unit
V
V
V
µs
ms
µs
µs
ms
kHz
µs
Parameter
Symbol Test Condition
Min Typ Max Units
Write Time1 ,2
tWRITE
One Byte,
FSYSCLK = 24.5 MHz
19 20 21 µs
Erase Time1 ,2
tERASE
One Page,
FSYSCLK = 24.5 MHz
5.2 5.35 5.5
ms
VDD Voltage During Programming3 VPROG
2.2 — 3.6 V
Endurance (Write/Erase Cycles) NWE
20k 100k
— Cycles
Note:
1. Does not include sequencing time before and after the write/erase operation, which may be multiple SYSCLK cycles.
2. The internal High-Frequency Oscillator has a programmable output frequency using the HFO0CAL register, which is factory pro-
grammed to 24.5 MHz. If user firmware adjusts the oscillator speed, it must be between 22 and 25 MHz during any flash write or
erase operation. It is recommended to write the HFO0CAL register back to its reset value when writing or erasing flash.
3. Flash can be safely programmed at any voltage above the supply monitor threshold (VVDDM).
4. Data Retention Information is published in the Quarterly Quality and Reliability Report.
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