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PDF PSMN0R7-25YLD Data sheet ( Hoja de datos )
| Número de pieza | PSMN0R7-25YLD | |
| Descripción | N-channel MOSFET | |
| Fabricantes | NXP Semiconductors | |
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PSMN0R7-25YLD
N-channel 25 V, 0.7 mΩ logic level MOSFET in LFPAK56
using NextPowerS3 Technology
15 April 2015
Objective data sheet
1. General description
Logic level gate drive N-channel enhancement mode MOSFET in LFPAK56 package.
NextPowerS3 portfolio utilising NXP's unique "SchottkyPlus" technology delivers
high efficiency, low spiking performance usually associated with MOSFETS with an
integrated Schottky or Schottky-like diode but without problematic high leakage current.
NextPowerS3 is particularly suited to high efficiency applications at high switching
frequencies.
2. Features and benefits
• Ultra low QG, QGD and QOSS for high system efficiency, especially at higher switching
frequencies
• Superfast switching with soft-recovery; s-factor > 1
• Low spiking and ringing for low EMI designs
• Unique "SchottkyPlus" technology; Schottky-like performance with < 1 μA leakage at
25 °C
• Optimised for 4.5 V gate drive
• Low parasitic inductance and resistance
• High reliability clip bonded and solder die attach Power SO8 package; no glue, no
wire bonds, qualified to 150 °C
• Wave solderable; exposed leads for optimal visual solder inspection
3. Applications
• On-board DC:DC solutions for server and telecommunications
• Secondary-side synchronous rectification in telecommunication applications
• Voltage regulator modules (VRM)
• Point-of-Load (POL) modules
• Power delivery for V-core, ASIC, DDR, GPU, VGA and system components
• Brushed and brushless motor control
• Power OR-ing
4. Quick reference data
Table 1.
Symbol
VDS
ID
Ptot
Quick reference data
Parameter
Conditions
drain-source voltage 25 °C ≤ Tj ≤ 150 °C
drain current
Tmb = 25 °C; VGS = 10 V
total power dissipation Tmb = 25 °C; Fig. 1
Min Typ Max Unit
- - 25 V
[1] - - 100 A
- - 291 W
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NXP Semiconductors
PSMN0R7-25YLD
N-channel 25 V, 0.7 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
9. Characteristics
Table 6. Characteristics
Symbol
Parameter
Conditions
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
VGS(th)
gate-source threshold ID = 2 mA; VDS = VGS; Tj = 25 °C
voltage
ΔVGS(th)/ΔT
gate-source threshold
voltage variation with
temperature
25 °C ≤ Tj ≤ 150 °C
IDSS drain leakage current VDS = 20 V; VGS = 0 V; Tj = 25 °C
VDS = 20 V; VGS = 0 V; Tj = 125 °C
IGSS gate leakage current VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
RDSon
drain-source on-state
resistance
VGS = 4.5 V; ID = 25 A; Tj = 25 °C
VGS = 4.5 V; ID = 25 A; Tj = 150 °C
VGS = 10 V; ID = 25 A; Tj = 25 °C
VGS = 10 V; ID = 25 A; Tj = 150 °C
RG
gate resistance
f = 1 MHz
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 12 V; VGS = 10 V;
Fig. 4
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
Fig. 4
ID = 0 A; VDS = 0 V; VGS = 10 V
QGS
QGS(th)
gate-source charge
pre-threshold gate-
source charge
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
Fig. 4
QGS(th-pl)
post-threshold gate-
source charge
QGD gate-drain charge
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 12 V; Fig. 4
Ciss
input capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C
Crss reverse transfer
capacitance
PSMN0R7-25YLD
Objective data sheet
All information provided in this document is subject to legal disclaimers.
15 April 2015
Min Typ Max Unit
25 - - V
22.5 - - V
1.2 1.7 2.2 V
- [tbd] - mV/K
- - 1 µA
- [tbd] - µA
- - 100 nA
- - 100 nA
- 0.72 0.9 mΩ
- - [tbd] mΩ
- 0.56 0.7 mΩ
- - [tbd] mΩ
- 1.4 - Ω
- 106.4 - nC
- 49 - nC
- 56.1 - nC
- 18.3 - nC
- 11.7 - nC
- 6.6 - nC
- 10.8 - nC
- 2.6 - V
- 8013 - pF
- 3242 - pF
- 484 - pF
© NXP Semiconductors N.V. 2015. All rights reserved
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