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PCU9661 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCU9661
Beschreibung Parallel bus to 1 channel UFm I2C-bus controller
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCU9661 Datasheet, Funktion
PCU9661
Parallel bus to 1 channel UFm I2C-bus controller
Rev. 1 — 12 September 2011
Product data sheet
1. General description
The PCU9661 is an advanced single master mode I2C-bus controller. It is a fourth
generation bus controller designed for data intensive I2C-bus data transfers. It has a
transmit only transfer rate of up to 5 Mbits/s using the new Ultra Fast-mode (UFm) bus
with push-pull topology. The serial channel has a generous 4352 byte data buffer which
makes the PCU9661 the ideal companion to any CPU that needs to transmit and receive
large amounts of serial data with minimal interruptions.
The PCU9661 is an 8-bit parallel-bus to I2C-bus protocol converter. It can be configured to
communicate with up to 64 slaves in one serial sequence with no intervention from the
CPU. The controller also has a sequence loop control feature that allows it to
automatically retransmit a stored sequence.
Its onboard oscillator and PLL allow the controller to generate the clocks for the I2C-bus
and for the interval timer used in sequence looping. This feature greatly reduces CPU
overhead when data refresh is required in fault tolerant applications.
An external trigger input allows data synchronization with external events. The trigger
signal controls the rate at which a stored sequence is re-transmitted over the I2C-bus.
Error reporting is handled at the transaction level, channel level, and controller level.
A simple interrupt tree and interrupt masks allow further customization of interrupt
management.
The controller parallel bus interface runs at 3.3 V and the I2C-bus I/Os logic levels are
referenced to a dedicated VDD(IO) input pin with a range of 3.0 V to 5.5 V.
2. Features and benefits
Parallel-bus to I2C-bus protocol converter and interface
5 Mbit/s unidirectional data transfer Ultra Fast-mode (UFm) channel (push-pull driver)
Internal oscillator trimmed to 1 % accuracy reduces external components
4352-byte UFm channel buffer
Three levels of reset: software channel reset, global software reset on parallel bus,
global hardware RESET pin
Communicates with up to 64 slaves in one serial sequence
Sequence looping with interval timer
JTAG port available for boundary scan testing during board manufacturing process
Trigger input synchronizes serial communication exactly with external events
Maskable interrupts
Operating supply voltage: 3.0 V to 3.6 V (device and host interface)






PCU9661 Datasheet, Funktion
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I2C-bus controller
7. Functional description
7.1 General
The PCU9661 acts as an interface device between standard high-speed parallel buses
and the serial I2C-bus. On the I2C-bus, it acts as a master. Data transfer between the
I2C-bus and the parallel-bus host is carried out on a buffered basis, using either an
interrupt or polled handshake.
7.2 Internal oscillator and PLL
The PCU9661 contains an internal 12.0 MHz oscillator and 156 MHz PLL which are used
for all internal and I2C-bus timing. The oscillator and PLL require up to tinit(po) to start up
and lock after power-up. The oscillator is not shut down if the serial bus is disabled.
7.3 Buffer description
Remark: In the following section a ‘transaction’ is defined as a contiguous set of
commands and/or data sent/received to/from a single slave. A ‘sequence’ is a set of
transactions stored in the buffer.
The PCU9661 serial channel has a 4352-byte data buffer (see Section 7.3.2 “Buffer size”)
that allows several transactions to be executed before an interrupt is generated. This
allows the host to request several transactions (up to maximum buffer size on each
channel) in a single sequence and lets the PCU9661 perform it without the intervention of
the host each time a requested transaction is performed. The host can then perform other
tasks while the PCU9661 executes the requested sequences.
By following a simple procedure, the I2C-bus controller can store several I2C-bus
transactions directed to different slaves addresses on any of the channels. Let us
consider the scenario where the host has done the initialization (mode, masks, and other
configuration) and writes data into the buffer.
The host starts by programming the buffer configuration registers TRANCONFIG (number
of slaves and bytes per slave) and then the SLATABLE (slave addresses). Then the host
programs the TRANSEL (Transaction Data Buffer Selection) and the TRANOFS (byte
offset selection) to 00h to set the memory pointers to the beginning of the buffer (the
default value is 00h after a power-on or RESET). Next, the host transfers the data into
DATA until the entire sequence is loaded.
Care should be taken so as to not overflow the buffer with excessive read/write
commands. In the event of an overflow, represented by the BE bit in the CTRLSTATUS
register, will be set to logic 1. The INT pin will be set LOW if the BEMSK bit in the
CTRLINTMSK register is logic 0. To recover the channel, a channel reset is required. All
configuration and data needs to be checked by the host and resent to the I2C-bus
controller. (See Section 7.3.2 “Buffer size”.)
After sending all the commands and data it wanted to the I2C-bus controller, the host
writes to the CONTROL register to begin data transmission on the serial channel. The
transactions will be sent on the I2C-bus in the order in which the slave addresses are
listed in the SLATABLE, separated by a RESTART condition. The last transaction in the
sequence will end with a STOP condition.
PCU9661
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 September 2011
© NXP B.V. 2011. All rights reserved.
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PCU9661 pdf, datenblatt
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I2C-bus controller
Table 5. CONTROL - Control register bit description …continued
Address: Channel 2 = E0h.
Legend: * reset value
Bit Symbol Access Value Description
3 TE
R/W
Trigger Enable (TE) bit controls the trigger input used for
frame refresh. TE cannot be changed while channel is
active. When the trigger input is enabled, the trigger will
override the contents of the FRAMECNT register and will
start triggering when STA bit is set. Thereafter, when a
trigger tick is detected, the controller will issue a START
command and the stored sequence will be transferred on
the serial bus.
1 When TE = 1, the sequence is controlled by the Trigger
input.
0* When TE = 0, the trigger inputs are ignored.
2 BPTRRST W
1 Resets auto increment pointers for BYTECOUNT. Reads
back as 0.
1 AIPTRRST W
1 Resets auto increment pointers for SLATABLE and
TRANCONFIG. The DATA register auto-increment pointer
will be set to the value that corresponds to TRANSEL and
TRANOFS registers. Reads back as 0.
Remark: To reset the data pointer, write 00h to TRANSEL.
0-
W 0 Reserved. User must write 0 to this bit.
Remark: Due to a small latency between setting the STA bit and the ability to detect a
trigger pulse, if the STA bit is set simultaneously to an incoming trigger pulse, the pulse
will be ignored and the controller will wait for the next trigger to send the START.
If the STO or STOSEQ bit are set at anytime while the STA bit is 0, then no action will be
taken and the write to these bits is ignored.
Remark: STO has priority over STOSEQ.
PCU9661
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 September 2011
© NXP B.V. 2011. All rights reserved.
12 of 52

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