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PCU9655 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCU9655
Beschreibung 16-channel UFm 5MHz bus 100mA 40V LED driver
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCU9655 Datasheet, Funktion
PCU9655
16-channel UFm 5 MHz bus 100 mA 40 V LED driver
Rev. 2 — 2 October 2012
Product data sheet
1. General description
The PCU9655 is a UFm I2C-bus controlled 16-channel LED driver optimized for voltage
switch dimming and blinking 100 mA Red/Green/Blue/Amber (RGBA) LEDs. Each LED
output has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller
that operates at approximately 31.25 kHz with a duty cycle that is adjustable from 0 % to
99.6 % to allow the LED to be set to a specific brightness value. An additional 8-bit
resolution (256 steps) group PWM controller has both a fixed frequency of about 122 Hz
and an adjustable frequency roughly between 15 Hz to once every 16.8 seconds with a
duty cycle that is adjustable from 0 % to 99.6 % that is used to either dim or blink all LEDs
with the same value.
Each LED output can be off, on (no PWM control), set at its individual PWM controller
value or at both individual and group PWM controller values. The PCU9655 operates with
a supply voltage range of 3 V to 5.5 V and the 100 mA open-drain outputs allow voltages
up to 40 V.
The PCU9655 is one of the first LED controller devices in a new Ultra Fast mode (UFm)
family. UFm devices offer higher frequency (up to 5 MHz).
Software programmable LED Group and three Sub Call I2C-bus addresses allow all or
defined groups of PCU9655 devices to respond to a common I2C-bus address, allowing
for example, all red LEDs to be turned on or off at the same time, thus minimizing I2C-bus
commands. On power-up, PCU9655 will have a unique Sub Call address to identify it as a
16-channel LED driver. This allows mixing of devices with different channel widths. Five
hardware address pins on PCU9655 allow up to 32 devices on the same bus.
The Software Reset (SWRST) function allows the master to perform a reset of the
PCU9655 through the I2C-bus, identical to the Power-On Reset (POR) that initializes the
registers to their default state causing the output voltage switches to be OFF (LED off).
This allows an easy and quick way to reconfigure all device registers to the same
condition.
Additionally, a thermal shutdown feature protects the device when the internal junction
temperature exceeds the overtemperature threshold.






PCU9655 Datasheet, Funktion
NXP Semiconductors
PCU9655
16-channel UFm 5 MHz bus 100 mA 40 V LED driver
slave address
W (write only)
1 1 A4 A3 A2 A1 A0 0
fixed
hardware selectable
002aaf631
Fig 3. PCU9655 slave address
The last bit of the address byte defines the operation to be performed. Only writes to
PCU9655 are supported, therefore the last bit is set to 0.
7.1.2 LED All Call UFm I2C-bus address
Default power-up value (ALLCALLADR register): A0h or 1010 000X
Programmable through I2C-bus (volatile programming)
At power-up, LED All Call I2C-bus address is enabled
See Section 7.3.9 “ALLCALLADR, LED All Call I2C-bus address” for more detail.
Remark: The default LED All Call I2C-bus address (A0h or 1010 000X) must not be used
as a regular I2C-bus slave address since this address is enabled at power-up. All of the
PCU9655s on the UFm I2C-bus will respond to the address if sent by the I2C-bus master.
7.1.3 LED Sub Call UFm I2C-bus addresses
3 different I2C-bus addresses can be used
Default power-up values:
SUBADR1 register: ACh or 1010 110X
SUBADR2 register: ACh or 1010 110X
SUBADR3 register: ACh or 1010 110X
Programmable through UFm I2C-bus (volatile programming)
At power-up, SUBADR1 is enabled while SUBADR2 and SUBADR3 I2C-bus
addresses are disabled.
Remark: At power-up SUBADR1 identifies this device as a 16-channel driver.
See Section 7.3.8 “SUBADR[3:1] LED Sub Call UFm I2C-bus addresses for PCU9655” for
more detail.
Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus
slave addresses as long as they are disabled in bit [3:1] = 000 of MODE1 register.
7.2 Control register
Following slave address, LED All Call address or LED Sub Call address, the bus master
will send a byte to the PCU9655, which will be stored in the Control register.
The lowest 7 bits are used as a pointer to determine which register will be accessed
(D[6:0]). The highest bit is used as Auto-Increment Flag (AIF). The AIF is active by default
at power-up.
PCU9655
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 October 2012
© NXP B.V. 2012. All rights reserved.
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PCU9655 pdf, datenblatt
NXP Semiconductors
PCU9655
16-channel UFm 5 MHz bus 100 mA 40 V LED driver
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
define a global blinking pattern, where GRPFREQ contains the blinking period (from
15 Hz to 16.8 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
duty cycle = G-----D-----C-------7---:--0----
256
(1)
7.3.5 GRPFREQ, group frequency
Table 9. GRPFREQ - Group frequency register (address 09h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value
Description
09h GRPFREQ 7:0 GFRQ[7:0] W only 0000 0000* GRPFREQ register
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3
registers).
Blinking period is controlled through 256 linear steps from 00h (67 ms, frequency 15 Hz)
to FFh (16.8 s).
global
blinking
period
=
G-----F----R----Q-------7----:--0-------+-----1-
15.26
s
(2)
7.3.6 PWM0 to PWM15, individual brightness control
Table 10. PWM0 to PWM15 - PWM registers 0 to 15 (address 0Ah to 19h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value
Description
0Ah PWM0 7:0 IDC0[7:0] W only 0000 0000* PWM0 Individual Duty Cycle
0Bh PWM1 7:0 IDC1[7:0] W only 0000 0000* PWM1 Individual Duty Cycle
0Ch PWM2 7:0 IDC2[7:0] W only 0000 0000* PWM2 Individual Duty Cycle
0Dh PWM3 7:0 IDC3[7:0] W only 0000 0000* PWM3 Individual Duty Cycle
0Eh PWM4 7:0 IDC4[7:0] W only 0000 0000* PWM4 Individual Duty Cycle
0Fh PWM5 7:0 IDC5[7:0] W only 0000 0000* PWM5 Individual Duty Cycle
10h PWM6 7:0 IDC6[7:0] W only 0000 0000* PWM6 Individual Duty Cycle
11h PWM7 7:0 IDC7[7:0] W only 0000 0000* PWM7 Individual Duty Cycle
12h PWM8 7:0 IDC8[7:0] W only 0000 0000* PWM8 Individual Duty Cycle
13h PWM9 7:0 IDC9[7:0] W only 0000 0000* PWM9 Individual Duty Cycle
14h PWM10 7:0 IDC10[7:0] W only 0000 0000* PWM10 Individual Duty Cycle
15h PWM11 7:0 IDC11[7:0] W only 0000 0000* PWM11 Individual Duty Cycle
16h PWM12 7:0 IDC12[7:0] W only 0000 0000* PWM12 Individual Duty Cycle
17h PWM13 7:0 IDC13[7:0] W only 0000 0000* PWM13 Individual Duty Cycle
18h PWM14 7:0 IDC14[7:0] W only 0000 0000* PWM14 Individual Duty Cycle
19h PWM15 7:0 IDC15[7:0] W only 0000 0000* PWM15 Individual Duty Cycle
PCU9655
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 October 2012
© NXP B.V. 2012. All rights reserved.
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