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W94AD6KB Schematic ( PDF Datasheet ) - Winbond

Teilenummer W94AD6KB
Beschreibung 1Gb Mobile LPDDR
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W94AD6KB Datasheet, Funktion
W94AD6KB / W94AD2KB
1Gb Mobile LPDDR
Table of Contents-
1. GENERAL DESCRIPTION .................................................................................................................................4
2. FEATURES ........................................................................................................................................................4
3. ORDER INFORMATION ....................................................................................................................................5
4. BALL CONFIGURATION....................................................................................................................................6
4.1 Ball Assignment: LPDDR x16 ...............................................................................................................6
4.2 Ball Assignment: LPDDR x32 ...............................................................................................................6
5. BALL DESCRIPTION .........................................................................................................................................7
5.1 Signal Descriptions...............................................................................................................................7
5.2 Addressing Table..................................................................................................................................8
6. BLOCK DIAGRAM..............................................................................................................................................9
6.1 Block Diagram ......................................................................................................................................9
6.2 Simplified State Diagram ....................................................................................................................10
7. FUNCTIONAL DESCRIPTION .........................................................................................................................11
7.1 Initialization.........................................................................................................................................11
7.1.1 Initialization Flow Diagram....................................................................................................12
7.1.2 Initialization Waveform Sequence ........................................................................................13
7.2 Mode Register Set Operation .............................................................................................................13
7.3 Mode Register Definition ....................................................................................................................14
7.3.1 Burst Length .........................................................................................................................14
7.3.2 Burst Definition .....................................................................................................................15
7.3.3 Burst Type ............................................................................................................................16
7.3.4 Read Latency .......................................................................................................................16
7.4 Extended Mode Register Description .................................................................................................16
7.4.1 Extended Mode Register Definition ......................................................................................17
7.4.2 Partial Array Self Refresh .....................................................................................................17
7.4.3 Automatic Temperature Compensated Self Refresh ............................................................17
7.4.4 Output Drive Strength...........................................................................................................17
7.5 Status Register Read .........................................................................................................................18
7.5.1 SRR Register Definition........................................................................................................18
7.5.2 Status Register Read Timing Diagram .................................................................................19
7.6 Commands .........................................................................................................................................20
7.6.1 Basic Timing Parameters for Commands .............................................................................20
7.6.2 Truth Table Commands..................................................................................................20
7.6.3 Truth Table - DM Operations................................................................................................21
7.6.4 Truth Table CKE.............................................................................................................21
7.6.5 Truth Table - Current State Bank n - Command to Bank n...................................................22
7.6.6 Truth Table - Current State Bank n, Command to Bank m ...................................................23
8. OPERATION ....................................................................................................................................................25
8.1 Deselect .............................................................................................................................................25
8.2 No Operation ......................................................................................................................................25
8.2.1 NOP Command ....................................................................................................................25
8.3 Mode Register Set..............................................................................................................................26
8.3.1 Mode Register Set Command ..............................................................................................26
8.3.2 Mode Register Set Command Timing...................................................................................26
Publication Release Date: Oct. 02, 2014
Revision: A01-005
-1-






W94AD6KB Datasheet, Funktion
W94AD6KB / W94AD2KB
4. BALL CONFIGURATION
4.1 Ball Assignment: LPDDR x16
60 BALL VFBGA
1
2
3 456
7
8
A
VSS
DQ15 VSSQ
VDDQ DQ0
B VDDQ DQ13 DQ14
DQ1
DQ2
C VSSQ DQ11 DQ12
DQ3
DQ4
D VDDQ DQ9 DQ10
DQ5
DQ6
E VSSQ UDQS DQ8
DQ7 LDQS
F VSS UDM NC
A13 LDM
G CKE CK CK
WE CAS
H A9 A11 A12
J A6
A7 A8
K VSS A4 A5
CS
A10/AP
A2
BA0
A0
A3
(Top View) Ball Configuration
4.2 Ball Assignment: LPDDR x32
90 BALL VFBGA
1
2
3 45 6
7
8
A VSS DQ31 VSSQ
VDDQ DQ16
B VDDQ DQ29 DQ30
DQ17 DQ18
C VSSQ DQ27 DQ28
DQ19 DQ20
D VDDQ DQ25 DQ26
DQ21 DQ22
E VSSQ DQS3 DQ24
DQ23 DQS2
F
VDD
DM3
NC
NC DM2
G CKE CK CK
WE CAS
H A9 A11 A12
J A6 A7 A8
K
A4
DM1
A5
L VSSQ DQS1 DQ8
M VDDQ DQ9 DQ10
N VSSQ DQ11 DQ12
P VDDQ DQ13 DQ14
R VSS DQ15 VSSQ
CS
A10/AP
A2
DQ7
DQ5
DQ3
DQ1
VDDQ
BA0
A0
DM0
DQS0
DQ6
DQ4
DQ2
DQ0
(Top View) Ball Configuration
9
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VDD
RAS
BA1
A1
VDD
9
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSS
RAS
BA1
A1
A3
VDDQ
VSSQ
VDDQ
VSSQ
VDD
Publication Release Date: Oct. 02, 2014
Revision: A01-005
-6-

6 Page









W94AD6KB pdf, datenblatt
7.1.1 Initialization Flow Diagram
W94AD6KB / W94AD2KB
1 VDD and VDDQ Ramp: CKE must be held high
2 Apply stable clocks
3 Wait at least 200µs with NOP or DESELECT on command bus
4 PRECHARGE ALL
5 Assert NOP or DESELCT for tRP time
Issue two AUTO REFRESH commands each followed by
6 NOP or DESELECT commands for tRFC time
7 Configure Mode Register
8 Assert NOP or DESELECT for tMRD time
9 Configure Extended Mode Register
10 Assert NOP or DESELECT for tMRD time
11 LPDDR SDRAM is ready for any valid command
- 12 -
Publication Release Date: Oct. 02, 2014
Revision: A01-005

12 Page





SeitenGesamt 30 Seiten
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